intel: Improve N-way pixel hashing computation to handle pixel pipes with asymmetric processing power.
This reworks the intel_compute_pixel_hash_table_nway()
pixel pipe
hashing table computation helper to handle cases where some pixel
pipes have processing power different from the others, this is helpful
for Gfx12.7+ platforms where there are pixel pipes with 1 DSS as well
as pixel pipes with 2 DSSes, which currently can lead to a serious
performance bottleneck in the pixel pipes with lower processing power.
In order to avoid such a load imbalance the
intel_compute_pixel_hash_table_nway()
function will now take two pixel
pipe bitsets instead of one: Pixel pipes enabled on both bitsets will
appear with twice the frequency on the table as pixel pipes which only
appear on one bitset. See the comments below for more details on the
algorithm used to construct a pixel hashing table with the desired
properties.
With this change rendering performance improves by about 25% on a
fused MTL platform -- The list of specific configs this is expected to
show an improvement on is not included here though since the list is rather
long and some of the configs may still be embargoed or may never be
productized [sent the data to @llandwerlin in order to ease review though, including dumps
of the new hashing tables for a range of configs and some stats
showing the improved balancing across pixel pipes for each config], but in order to find out whether your Gfx12.7+ device
could be affected by this you can check the output of the
intel_dev_info
tool from the Mesa tree and see if there are multiple
"pixel pipe" entries with different DSS count. That isn't expected to
occur on any DG2 configuration, only on MTL+ platforms, so this change
should have no functional nor performance changes at all on DG2 even though it also uses the intel_compute_pixel_hash_table_nway()
codepath reworked here.