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freedreno,turnip: Update a690 magic regs and disable UBWC for D/S images

Danylo Piliaiev requested to merge Danil/mesa:freedreno/feature/a690 into main

What does this MR do and why?

Preface: I fixed hangs on a690 (#9246) with changes to kernel regs: (note, there is ubwc_mode = 2 which don't make much sense since ubwc_mode could be either 0 or 1, but Windows kernel driver sets REG_A6XX_RB_NC_MODE_CNTL to 0x00000816, though I didn't see any change if I don't set ubwc_mode). @robclark could you upstream these changes? I don't have any set up for kernel contributions, don't even know where to send patches =)

The changes in magic regs don't seem to fix anything, but now that's values from driver running on actual HW.

I also had to disable UBWC for D/S images. Not a fan of it... But there are many test failures with D/S and UBWC enabled. They are fixed by flushall, by depth flush in particular. The issue is that I don't see a reason for depth flush to be where I found it to fix the issues: mostly between ordinary draw calls which read/write depth in a renderpass.

Example of corruption in dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states.fail_repl.pass_decw.dfail_inv.comp_never:


I checked what WSL blob does: it passes more D/S tests than we, but still fail some for some reason. In some cases it uses UBWC in some it is not. But with tests running through VK->D3D12 layer I'm not sure if it's luck or not.

There are a bit more changes in a690 cmdstream compared to a660 e.g. blob:

  • Sets A6XX_GRAS_UNKNOWN_8110 to 2
  • Has RB_WINDOW_OFFSET2: { X = 0 | Y = 0 | 0xc000c000 }/SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 | 0xc000c000 } - I don't think it does anything.

And a few more changes in regs, but they don't seem to affect anything.

With all the changes there are still some issues in some games e.g. God of War 2018 has rendering corruption:

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