nir/trivialize_registers: Handle obscure load hazard
What does this MR do and why?
nir/trivialize_registers: Handle obscure load hazard
Somebody less tired than me would add a unit test for this. Offending snippet:
32 %58 = @load_reg (%55) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %57 = @load_reg (%55) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %21 = iadd %57, %15 (0x1)
@store_reg (%21, %55) (base=0, wrmask=x, legacy_fsat=0)
32 %56 = @load_reg (%55) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %22 = i2f32 %56
32 %23 = load_const (0x41000000 = 8.000000)
32 %24 = fdiv %22, %23 (8.000000)
32 %90 = mov %24
@store_reg_indirect (%90, %78, %58) (base=0, wrmask=x, legacy_fsat=0)
Closes: #10031 (closed) Fixes: d313eba9 ("nir: Add pass for trivializing register access") Signed-off-by: Alyssa Rosenzweig alyssa@rosenzweig.io Reported-by: Timothy Arceri tarceri@itsqueeze.com
@tarceri If this fixes it please merge. I do not have the spoons to interact with mesa ci.