etnaviv: nir: do not call nir_lower_idiv(..) unconditionally
What does this MR do and why?
etnaviv: nir: do not call nir_lower_idiv(..) unconditionally
There is no need to call it if we are calling nir_lower_int_to_float(..). Fixes nir crashes I am seeing with gc2000_gles2 CI job.
Here is one of the problems in more depth.
nir_lower_vars_to_ssa
shader: MESA_SHADER_FRAGMENT
source_sha1: {0xb4dfe80f, 0x93b7360f, 0xfddeaeba, 0xf8346894, 0x45606367}
name: GLSL1
label: shaders_val/deqp_gles2/15853.shader_test
stage: 4
next_stage: 4
inputs_read: 32-33
outputs_written: 2
subgroup_size: 1
bit_sizes_float: 0x20
bit_sizes_int: 0x20
flrp_lowered: true
inputs: 2
outputs: 1
uniforms: 0
decl_var shader_in INTERP_MODE_NONE mediump vec4 v_in0 (VARYING_SLOT_VAR0.xyzw, 0, 0)
decl_var shader_in INTERP_MODE_NONE mediump vec4 v_in1 (VARYING_SLOT_VAR1.xyzw, 1, 0)
decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0)
decl_function main (0 params)
impl main {
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
vec3 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location=VARYING_SLOT_VAR0 slots=1 mediump /*8388768*/) /* v_in0 */
vec1 32 ssa_2 = intrinsic load_input (ssa_0) (base=1, component=0, dest_type=float32 /*160*/, io location=VARYING_SLOT_VAR1 slots=1 mediump /*8388769*/) /* v_in1 */
vec1 32 ssa_3 = load_const (0x3f800000 = 1.000000)
vec1 32 ssa_4 = load_const (0x3d23d70a = 0.040000)
vec3 32 ssa_5 = f2i32 ssa_1.zxy
vec1 32 ssa_6 = f2i32 ssa_2
vec3 1 ssa_7 = ilt! ssa_5, ssa_0.xxx
vec1 1 ssa_8 = ilt! ssa_6, ssa_0
vec3 32 ssa_9 = iabs! ssa_5
vec1 32 ssa_10 = iabs! ssa_6
vec3 1 ssa_11 = ixor! ssa_7, ssa_8.xxx
vec1 32 ssa_12 = u2f32! ssa_10
vec1 32 ssa_13 = frcp! ssa_12
vec1 32 ssa_14 = load_const (0x4f7ffffe = 4294966784.000000)
vec1 32 ssa_15 = fmul! ssa_13, ssa_14
vec1 32 ssa_16 = f2u32! ssa_15
vec1 32 ssa_17 = imul! ssa_10, ssa_16
vec1 32 ssa_18 = ineg! ssa_17
vec1 32 ssa_19 = load_const (0x00000010 = 0.000000)
vec1 32 ssa_20 = load_const (0x0000ffff = 0.000000)
vec1 32 ssa_21 = iand! ssa_16, ssa_20
vec1 32 ssa_22 = iand! ssa_18, ssa_20
vec1 32 ssa_23 = ushr! ssa_16, ssa_19
vec1 32 ssa_24 = ushr! ssa_18, ssa_19
vec1 32 ssa_25 = imul! ssa_21, ssa_22
vec1 32 ssa_26 = imul! ssa_21, ssa_24
vec1 32 ssa_27 = imul! ssa_23, ssa_22
vec1 32 ssa_28 = imul! ssa_23, ssa_24
vec1 32 ssa_29 = load_const (0x00010000 = 0.000000)
vec1 32 ssa_30 = imul! ssa_26, ssa_29
vec1 32 ssa_31 = iadd! ssa_25, ssa_30
vec1 1 ssa_32 = ult! ssa_31, ssa_25
vec1 32 ssa_33 = b2i32! ssa_32
vec1 32 ssa_34 = iadd! ssa_28, ssa_33
vec1 32 ssa_35 = ushr! ssa_26, ssa_19
vec1 32 ssa_36 = iadd! ssa_34, ssa_35
vec1 32 ssa_37 = imul! ssa_27, ssa_29
vec1 32 ssa_38 = iadd! ssa_31, ssa_37
vec1 1 ssa_39 = ult! ssa_38, ssa_31
vec1 32 ssa_40 = b2i32! ssa_39
vec1 32 ssa_41 = iadd! ssa_36, ssa_40
vec1 32 ssa_42 = ushr! ssa_27, ssa_19
vec1 32 ssa_43 = iadd! ssa_41, ssa_42
vec1 32 ssa_44 = iadd! ssa_16, ssa_43
vec3 32 ssa_45 = iand! ssa_9, ssa_20.xxx
vec1 32 ssa_46 = iand! ssa_44, ssa_20
vec3 32 ssa_47 = ushr! ssa_9, ssa_19.xxx
vec1 32 ssa_48 = ushr! ssa_44, ssa_19
vec3 32 ssa_49 = imul! ssa_45, ssa_46.xxx
vec3 32 ssa_50 = imul! ssa_45, ssa_48.xxx
vec3 32 ssa_51 = imul! ssa_47, ssa_46.xxx
vec3 32 ssa_52 = imul! ssa_47, ssa_48.xxx
vec3 32 ssa_53 = imul! ssa_50, ssa_29.xxx
vec3 32 ssa_54 = iadd! ssa_49, ssa_53
vec3 1 ssa_55 = ult! ssa_54, ssa_49
vec3 32 ssa_56 = b2i32! ssa_55
vec3 32 ssa_57 = iadd! ssa_52, ssa_56
vec3 32 ssa_58 = ushr! ssa_50, ssa_19.xxx
vec3 32 ssa_59 = iadd! ssa_57, ssa_58
vec3 32 ssa_60 = imul! ssa_51, ssa_29.xxx
vec3 32 ssa_61 = iadd! ssa_54, ssa_60
vec3 1 ssa_62 = ult! ssa_61, ssa_54
vec3 32 ssa_63 = b2i32! ssa_62
vec3 32 ssa_64 = iadd! ssa_59, ssa_63
vec3 32 ssa_65 = ushr! ssa_51, ssa_19.xxx
vec3 32 ssa_66 = iadd! ssa_64, ssa_65
vec3 32 ssa_67 = imul! ssa_66, ssa_10.xxx
vec3 32 ssa_68 = ineg! ssa_67
vec3 32 ssa_69 = iadd! ssa_9, ssa_68
vec3 1 ssa_70 = uge! ssa_69, ssa_10.xxx
vec1 32 ssa_71 = load_const (0x00000001 = 0.000000)
vec3 32 ssa_72 = iadd! ssa_66, ssa_71.xxx
vec3 32 ssa_73 = bcsel! ssa_70, ssa_72, ssa_66
vec1 32 ssa_74 = ineg! ssa_10
vec3 32 ssa_75 = iadd! ssa_69, ssa_74.xxx
vec3 32 ssa_76 = bcsel! ssa_70, ssa_75, ssa_69
vec3 1 ssa_77 = uge! ssa_76, ssa_10.xxx
vec3 32 ssa_78 = iadd! ssa_73, ssa_71.xxx
vec3 32 ssa_79 = bcsel! ssa_77, ssa_78, ssa_73
vec3 32 ssa_80 = ineg! ssa_79
vec3 32 ssa_81 = bcsel! ssa_11, ssa_80, ssa_79
vec3 32 ssa_82 = i2f32 ssa_81
vec4 32 ssa_83 = vec4 ssa_82.x, ssa_82.y, ssa_82.z, ssa_3
vec4 32 ssa_84 = fmul ssa_83, ssa_4.xxxx
vec4 32 ssa_85 = fadd ssa_84, ssa_3.xxxx
vec1 32 ssa_86 = deref_var &gl_FragColor (shader_out vec4)
intrinsic store_deref (ssa_86, ssa_85) (wrmask=xyzw /*15*/, access=0)
/* succs: block_1 */
block block_1:
}
nir_opt_copy_prop_vars
nir_opt_shrink_stores
nir_opt_shrink_vectors
nir_copy_prop
nir_opt_dce
nir_opt_cse
nir_opt_peephole_select
nir_opt_intrinsics
nir_opt_algebraic
nir_opt_constant_folding
nir_opt_dead_cf
nir_opt_trivial_continues
nir_opt_loop_unroll
nir_opt_if
nir_opt_remove_phis
nir_opt_undef
nir_lower_int_to_float
vec1 32 ssa_21 = iand! ssa_16, ssa_20
run: ../src/compiler/nir/nir_lower_int_to_float.c:204: lower_alu_instr: Assertion `nir_alu_type_get_base_type(info->output_type) != nir_type_int && nir_alu_type_get_base_type(info->output_type) != nir_type_uint' failed.
=> CRASHED <= while processing these shaders: