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intel/dev: correct the VS urb max entry for DG2

Chuansheng Liu requested to merge chuansheng/mesa:fix_max_vs_urb into main

Now the default value is 3576 which is for Tgl, it should be 3832 for DG2 which can also be read out from HW config.

Signed-off-by: Chuansheng Liu chuansheng.liu@intel.com

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