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Draft: intel/nir: Use 32-bit loads for unaligned SSBO access and shift

We were previously doing this only in the case where we have a constant offset but we can also do it for non-constant offsets now as well. This should reduce the number of load instructions in shaders that use 8-bit things with non-constant offsets. We can now, for instance, load from a tightly packed uvec3 array with a single SEND instruction.

Marked as draft because, while it passes CTS, I have no numbers for it. There are no 8 or 16B things in GL so it'd have to be Vulkan or CL and I don't have a good database for those at the moment.

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