iris: Don't reject CPU access for non-invalidating buffer write maps

Buffer maps that don't invalidate their destination range work better as direct CPU maps than staging blits. The application may write only part of the range, effectively combining the new data with existing data. So even if the map would stall, the staging blit path won't help us, as we have to read the existing data to populate the staging buffer before returning it. This incurs a stall anyway - plus a read and copy.

In contrast, a direct map doesn't need to read any data - it can just write the destination and the existing data will still be there.

Fixes excessive blits for stalling buffer writes that don't invalidate the buffer since my recent map heuristic rework.

Fixes: bec68a85 ("iris: Improve direct CPU map heuristics") Closes: #7895 (closed)