Skip to content

freedreno/crashdec: Handle multi-IB prefetching

Connor Abbott requested to merge cwabbott0/mesa:review/fd-crashdec-prefetch-ib into main

This is an optimization in the command processor firmware where several indirect buffer packet are effectively combined into one and the ROQ may prefetch from later IB's before the first IB in the sequence is finished. This significantly complicates figuring out where the CP is, because we can't just add the prefetched data to REM anymore and instead have to walk back to a previous IB. There are also a few complications and gotchas that make things even worse:

  • This may happen recursively, i.e. a sequence of IB2's that spans multiple IB1's may get combined if those IB1's were also combined.
  • We still have to support multiple IB2's within a single IB1. Previously we handled this by refusing to trigger on an address inside an IB2 until the address of the IB2 call itself in IB1 was already triggered. However if the IB2's are combined then the CP may be ahead of the actual IB2 being processed in the IB1. This may happen regardless of how far ahead the ROQ is.

We handle this by trying to emulate what the CP does, walking forward until we find a "matching" IB2, and then adjusting the base/rem to get the "final" one which highlight_gpuaddr now uses.

I also added some new CP debug registers that were useful for debugging problems with this.

Merge request reports