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radeonsi/gfx10: fix sgpr/vgpr hardware limit computation

Pierre-Eric Pelloux-Prayer requested to merge pepp/mesa:radeonsi_fix_vgpr into master
  • gfx10 has more vgpr per simd
  • when using wave64 we get half the wave count but registers must be counted twice
  • make it explicit that we're using WGP mode

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