nir_to_tgsi: Make vec_to_movs avoid unsupported coalescing for 64-bit.

I had some workarounds in ALU op emits trying to fix up when we were asked to store to unsupported channels when the ALU op had 64bit srcs (so only vec2 supported) but a 32-bit dest with a >vec2 writemask.

Those workarounds had some bugs breaking 64-bit uniform initializer tests on virgl, and also set up too wide of a writemask such that they triggered assertion failures on nvc0. We can avoid the need for those workarounds at emit time by just having nir_lower_vec_to_movs not generate unsupported writemasks in the first place.