freedreno/a6xx: Fix SP_DS_CTRL_REG0 definition

Bit 20 isn't actually MERGEDREGS, the mode for the entire geometry pipeline is controlled by SP_VS_CTRL_REG0::MERGEDREGS and it appears to be something preamble-related instead since writing any register in the preamble hangs if it's set. This fixes those hangs on freedreno and turnip since we no longer set it.

Fixes: fccc35c2 ("ir3: Add preamble optimization pass")