lima/ppir: support pipeline registers in scheduler

The ppir scheduler grew to be rather complicated and containing many exceptions as it also has to take care of inserting additional nodes when it is mandatory for nodes to be in the same instruction. As such, the lima lowering and scheduling process can be difficult to understand and maintain. The ppir lowering step created nodes hoping that the scheduler would notice the exception and do the right thing.

This proposal adds a simple refactor to the scheduler so that it places nodes with pipeline registers in the same instruction. With the scheduler handling this in a general way, it is possible to create same-instruction dependencies by using pipeline registers during the lowering stage. This is (hopefully) simpler to maintain because now we can make these dependencies explicit in a single place (lowering), and we can drop exceptions from scheduling.

Reducing the complexity of the scheduler is also useful as preparatory work to support control flow in ppir.