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intel/fs: Rework fence handling and enable URB fences on LSC platforms

Faith Ekstrand requested to merge gfxstrand/mesa:wip/intel-barrier-refactor into main

This MR is extracted from !4743 (merged) and contains some refactors to the Intel back-end which affect all platforms but are particularly important for platforms with LSC. The last two patches are untested but add the URB fence message and hook it up for TCS output barriers on LSC platforms. We seemed to have missed this during platform enabling.

@cmarcelo @sagarghuge and @jljusten for review and testing.

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