Draft: freedreno/ir3: pre-RA scheduler tuning
Looking at #5307 (closed) I noticed that pre-RA sched was making a proper mess of the attached shader. The problem was that it was preferring picking an instruction that wouldn't defer but increased register pressure over an instruction that would defer but decreased register pressure (or was neutral). We probably want to prioritize reducing register pressure harder in pre-RA scheduling.
Marked as draft because I've not had time to go thru all of shader-db and perf traces tests yet, and a bit undecided on the last two patches. But probably the current limit of 8 outstanding tex fetches is too high.