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ci/radeonsi: Mark a glx_arb_sync_control/timing flake.

Emma Anholt requested to merge anholt/mesa:ci-radeonsi-flake into master

I've seen this one happen at least twice today. Log shows something like:

Wallclock time between MSCs 16982.888889us does not match
glXGetMscRateOML 16668.071966us

or

Wallclock time between MSCs 16500.333333us does not match
glXGetMscRateOML 16668.071966us

Incidentally, both runs I've looked into had one run too fast and one run too slow.

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