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ac,radeonsi: DCC retiling rework, direct HTILE fast clears, mipmapped fast clears, full DCC MSAA on GFX9

Marek Olšák requested to merge mareko/mesa:si-clear-retile into master

Moved from !9795 (merged).

  • DCC retiling reworked not to use the retile map (it's faster now).
    • There is a CPU version of DccAddrFromCoord as a test (which might not build in CI) and a NIR version of the same. The retile shader is in NIR.
    • DCC address equations are added into radeon_surf.
    • RADV code is disabled, but should be easy to enable the new codepath. Drivers only need only 1 shader variant despite ac_surface being used to generate the shader.
  • Direct HTILE clears added and are parallelized with DCC/CMASK clears. Z-only and S-only HTILE clears via a read-modify-write compute shader are also added.
  • All explicit DCC/CMASK/HTILE clears support mipmapping with some limitations. (CMASK - only one level in a mipmap tree, DCC and HTILE - any non-array level)
  • GFX9 receives full DCC MSAA support (using a compute shader and DCC equations to clear 4x and 8x MSAA buffers)

Tested piglit/glcts/deqp:

  • gfx6-7
  • gfx8 (Polaris11)
  • gfx9: (Vega10; Only MSAA: Raven)
  • gfx10: (Navi14)
  • gfx10.3 (Sienna)

Tested DCC retiling:

  • gfx9 (Raven)
  • gfx10 (Navi14)
  • gfx10.3 (Sienna)
Edited by Marek Olšák

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