intel: Implement compiler support for XeHP graphics platforms.

This MR implements compiler support for the ISA of the Intel XeHP family of GPUs. The most invasive compiler changes relative to previous generations are the result of the preexisting FPU pipeline being split into multiple asynchronous pipelines (a floating-point, integer and long AKA double-precision pipeline), which is highly visible to software because the hardware is not able to guarantee data coherency across instructions (already since TGL), so the compiler is now responsible for keeping track of which pipeline will be executing which instruction and specifying synchronization primitives in order to resolve any cross-pipeline dependencies. This is the purpose of the SWSB-related patches at the beginning of this series that extend the existing software scoreboard lowering pass in order to handle multiple in-order pipelines and cross-pipeline dependencies.

A good chunk of the remaining changes are required in order to address the restrictions of the newly introduced pipelines. The floating-point and long pipelines will no longer be able to support arbitrary regioning, requiring destination-aligned source regions similar to the restrictions of previous CHV and BXT platforms, but now affecting single-precision float instructions as well. Addressing this involves, among other things, some extensions of the regioning lowering pass and adding a new lowering pass for derivative operations which previously relied on floating-point arithmetic with non-trivial regioning modes.