mesa 23.1.0-rc3 flickering textures/lighting in Unreal 4 games Polaris10
AMD RX 570 Polaris10 Linux 6.3.0 (amdgpu) Distro: Manjaro-Arch (customized) X11 (not Wayland)
I got off the main branch at 23.1.0-rc2 and used that up until 22.1.0-rc3 was tagged, at which time I discovered flashing textures, surfaces, and lighting in Unreal 4 games. It was most noticeable immediately on the main menu screen on Borderlands 3, and in game immediately with objects like vending machines. Also noticeable in the new Star Wars Jedi Survivor game, both in main menu and in game. Both of those DirectX 12 (I did not test any Unreal 4/DirectX 11 games)
Going back to my 23.1.0-rc2 build, it was back to normal. Unfortunate that so much time and so many commits to the main branch had occurred between my builds.
To identify what broke me, I switched to the main branch again, 23.2.0
I (sort of) bisected it, and definitively narrowed it down to this commit, for me.
commit d44651bf radv: wait for occlusion queries in the resolve query shader ("one week ago" it said in the web interface...)
I then did "git revert d44651bf" and built, and the problem was again solved.
So then, against mesa-23.1.0-rc3, this fixes it for me. Tested with Borderlands 3 in menu and in game
--- mesa_orig/src/amd/vulkan/radv_query.c 2023-05-02 21:40:28.558408436 -0400
+++ mesa/src/amd/vulkan/radv_query.c 2023-05-02 21:57:53.019473703 -0400
@@ -139,31 +139,6 @@
nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
nir_store_var(&b, available, nir_imm_true(&b), 0x1);
- nir_ssa_def *query_result_wait = nir_test_mask(&b, flags, VK_QUERY_RESULT_WAIT_BIT);
- nir_push_if(&b, query_result_wait);
- {
- /* Wait on the upper word of the last DB entry. */
- nir_push_loop(&b);
- {
- const uint32_t rb_avail_offset = 16 * util_last_bit64(enabled_rb_mask) - 4;
-
- /* Prevent the SSBO load to be moved out of the loop. */
- nir_scoped_memory_barrier(&b, NIR_SCOPE_INVOCATION, NIR_MEMORY_ACQUIRE, nir_var_mem_ssbo);
-
- nir_ssa_def *load_offset = nir_iadd_imm(&b, input_base, rb_avail_offset);
- nir_ssa_def *load = nir_load_ssbo(&b, 1, 32, src_buf, load_offset, .align_mul = 4,
- .access = ACCESS_COHERENT);
-
- nir_push_if(&b, nir_ige(&b, load, nir_imm_int(&b, 0x80000000)));
- {
- nir_jump(&b, nir_jump_break);
- }
- nir_pop_if(&b, NULL);
- }
- nir_pop_loop(&b, NULL);
- }
- nir_pop_if(&b, NULL);
-
nir_push_loop(&b);
nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
@@ -1566,6 +1541,19 @@
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
+ if (flags & VK_QUERY_RESULT_WAIT_BIT) {
+ uint64_t enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask;
+ uint32_t rb_avail_offset = 16 * util_last_bit64(enabled_rb_mask) - 4;
+ for (unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
+ unsigned query = firstQuery + i;
+ uint64_t src_va = va + query * pool->stride + rb_avail_offset;
+
+ radeon_check_space(cmd_buffer->device->ws, cs, 7);
+
+ /* Waits on the upper word of the last DB entry */
+ radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va, 0x80000000, 0xffffffff);
+ }
+ }
radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
pool->bo, dst_buffer->bo, firstQuery * pool->stride,
dst_buffer->offset + dstOffset, pool->stride, stride, dst_size, queryCount,