freedreno/ir3: deref not getting lowered in spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-index-wr-before-tcs
Was taking a quick peek piglit regressions when we enable GL_ARB_gpu_shader_fp64, and this one looks pretty unrelated (ie. s/dvec4/vec4/g
still has same issue). The issue actually appears to be an issue with indirect output store. If the VS write to blk.vs_var0[index]
is removed we don't hit the issue. (See https://gitlab.freedesktop.org/mesa/piglit/-/blob/main/tests/spec/arb_tessellation_shader/execution/variable-indexing/vs-output-array-dvec4-index-wr-before-tcs.shader_test#L24.) It seems like this prevents nir_lower_vars_to_ssa
from lowering the store_deref
/load_deref
, which persists until nir->ir3 which is not expecting to encounter derefs.
Edited by Rob Clark