...
2022-07-27 22:49:39.458298: succ get_rt_readback Failed to get surface desc, hr 0.
2022-07-27 22:49:39.458305: NIR (SSA form) for vertex shader:
2022-07-27 22:49:39.458314: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:39.458322: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:39.458330: name: TTN
2022-07-27 22:49:39.458337: inputs: 3
2022-07-27 22:49:39.458345: outputs: 4
2022-07-27 22:49:39.458352: uniforms: 0
2022-07-27 22:49:39.458359: ubos: 1
2022-07-27 22:49:39.458366: shared: 0
2022-07-27 22:49:39.458373: ray queries: 0
2022-07-27 22:49:39.458380: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:39.458387: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:39.458395: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:39.458402: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:39.458409: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:39.458417: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:39.458424: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:39.458431: decl_var uniform INTERP_MODE_NONE vec4[4] uniform_0 (0, 0, 0)
2022-07-27 22:49:39.458438: decl_var ubo INTERP_MODE_NONE vec4[4] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:39.458446: decl_function main (0 params)
2022-07-27 22:49:39.458453: impl main {
2022-07-27 22:49:39.458460: block block_0:
2022-07-27 22:49:39.458468: /* preds: */
2022-07-27 22:49:39.458475: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:39.458482: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:39.458490: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:39.458498: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:39.458506: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:39.458513: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:39.458520: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:39.458528: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:39.458535: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:39.458543: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:39.458550: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:39.458557: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:39.458564: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:39.458571: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:39.458578: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:39.458585: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:39.458592: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:39.458599: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:39.458666: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:39.458678: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:39.458685: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:39.458692: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:39.458699: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:39.458727: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:39.458734: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:39.458742: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:39.458750: vec4 32 div ssa_26 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:39.458757: vec1 32 div ssa_27 = fsat ssa_26.x
2022-07-27 22:49:39.458764: vec1 32 div ssa_28 = fsat ssa_26.y
2022-07-27 22:49:39.458771: vec1 32 div ssa_29 = fsat ssa_26.z
2022-07-27 22:49:39.458778: vec1 32 div ssa_30 = fsat ssa_26.w
2022-07-27 22:49:39.458785: vec4 32 div ssa_31 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:39.458792: vec1 32 div ssa_32 = fsat ssa_31.x
2022-07-27 22:49:39.458799: vec1 32 div ssa_33 = fsat ssa_31.y
2022-07-27 22:49:39.458807: vec1 32 div ssa_34 = fsat ssa_31.z
2022-07-27 22:49:39.458814: vec1 32 div ssa_35 = fsat ssa_31.w
2022-07-27 22:49:39.458821: vec4 32 div ssa_36 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:39.458830: intrinsic store_output (ssa_36, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:39.458839: vec4 32 div ssa_37 = vec4 ssa_27, ssa_28, ssa_29, ssa_30
2022-07-27 22:49:39.458846: intrinsic store_output (ssa_37, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:39.458853: vec4 32 div ssa_38 = vec4 ssa_32, ssa_33, ssa_34, ssa_35
2022-07-27 22:49:39.458861: intrinsic store_output (ssa_38, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:39.458868: vec4 32 div ssa_39 = vec4 ssa_31.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:39.458876: intrinsic store_output (ssa_39, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:39.458885: /* succs: block_1 */
2022-07-27 22:49:39.458893: block block_1:
2022-07-27 22:49:39.458900: }
2022-07-27 22:49:39.458908: NIR (final form) for vertex shader:
2022-07-27 22:49:39.458916: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:39.458924: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:39.458931: name: TTN
2022-07-27 22:49:39.458939: inputs: 3
2022-07-27 22:49:39.458946: outputs: 4
2022-07-27 22:49:39.458954: uniforms: 0
2022-07-27 22:49:39.458962: ubos: 1
2022-07-27 22:49:39.458970: shared: 0
2022-07-27 22:49:39.458989: ray queries: 0
2022-07-27 22:49:39.458997: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:39.459006: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:39.459015: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:39.459024: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:39.459033: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:39.459067: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:39.459078: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:39.459086: decl_var uniform INTERP_MODE_NONE vec4[4] uniform_0 (0, 0, 0)
2022-07-27 22:49:39.459094: decl_var ubo INTERP_MODE_NONE vec4[4] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:39.459103: decl_function main (0 params)
2022-07-27 22:49:39.459111: impl main {
2022-07-27 22:49:39.459120: block block_0:
2022-07-27 22:49:39.459128: /* preds: */
2022-07-27 22:49:39.459137: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:39.459146: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:39.459154: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:39.459163: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:39.459173: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:39.459203: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:39.459217: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.714250: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.714387: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.714404: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.714426: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.714436: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.714444: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.714453: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.714461: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.714470: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.714480: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.714489: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.714500: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.714510: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.714518: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.714527: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.714537: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.714545: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.714554: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.714562: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.714571: vec4 32 div ssa_26 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.714580: vec1 32 div ssa_27 = fsat ssa_26.x
2022-07-27 22:49:44.714589: vec1 32 div ssa_28 = fsat ssa_26.y
2022-07-27 22:49:44.714599: vec1 32 div ssa_29 = fsat ssa_26.z
2022-07-27 22:49:44.714608: vec1 32 div ssa_30 = fsat ssa_26.w
2022-07-27 22:49:44.714616: vec4 32 div ssa_31 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.714625: vec1 32 div ssa_32 = fsat ssa_31.x
2022-07-27 22:49:44.714634: vec1 32 div ssa_33 = fsat ssa_31.y
2022-07-27 22:49:44.714643: vec1 32 div ssa_34 = fsat ssa_31.z
2022-07-27 22:49:44.714652: vec1 32 div ssa_35 = fsat ssa_31.w
2022-07-27 22:49:44.714661: vec4 32 div ssa_36 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.714696: intrinsic store_output (ssa_36, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.714706: vec4 32 div ssa_37 = vec4 ssa_27, ssa_28, ssa_29, ssa_30
2022-07-27 22:49:44.714714: intrinsic store_output (ssa_37, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.714723: vec4 32 div ssa_38 = vec4 ssa_32, ssa_33, ssa_34, ssa_35
2022-07-27 22:49:44.714730: intrinsic store_output (ssa_38, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.714740: vec4 32 div ssa_39 = vec4 ssa_31.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.714748: intrinsic store_output (ssa_39, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.714757: /* succs: block_1 */
2022-07-27 22:49:44.714766: block block_1:
2022-07-27 22:49:44.714774: }
2022-07-27 22:49:44.714782: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.714791: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.714799: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.714808: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.714817: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.714825: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.714834: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.714843: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714851: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714859: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714867: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714876: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714883: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714891: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714899: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714908: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714917: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714926: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714934: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714944: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714952: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714960: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714969: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714978: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.714986: Native code for unnamed vertex shader TTN (sha1 48a99faba555e0b3c35cae172e890c310d24424e)
2022-07-27 22:49:44.714996: SIMD8 shader: 29 instructions. 0 loops. 114 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 464 to 352 bytes (24%)
2022-07-27 22:49:44.715005: START B0 (114 cycles)
2022-07-27 22:49:44.715013: mul(8) g24<1>F g4<8,8,1>F g2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715022: mul(8) g25<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715031: mul(8) g26<1>F g4<8,8,1>F g2.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715040: mul(8) g27<1>F g4<8,8,1>F g2.3<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715049: mov.sat(8) g16<1>F g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715057: mov.sat(8) g17<1>F g9<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715163: mov.sat(8) g18<1>F g10<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715175: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715206: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715224: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715234: mov.sat(8) g22<1>F g14<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715242: mov.sat(8) g23<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715251: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.715261: mad(8) g28<1>F g24<4,4,1>F g2.4<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715269: mad(8) g29<1>F g25<4,4,1>F g2.5<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715277: mad(8) g30<1>F g26<4,4,1>F g2.6<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715286: mad(8) g31<1>F g27<4,4,1>F g2.7<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715294: mad(8) g32<1>F g28<4,4,1>F g3.0<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715302: mad(8) g33<1>F g29<4,4,1>F g3.1<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715310: mad(8) g34<1>F g30<4,4,1>F g3.2<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715318: mad(8) g35<1>F g31<4,4,1>F g3.3<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715326: mad(8) g52<1>F g32<4,4,1>F g3.4<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715334: mad(8) g53<1>F g33<4,4,1>F g3.5<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715342: mad(8) g54<1>F g34<4,4,1>F g3.6<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715352: mad(8) g55<1>F g35<4,4,1>F g3.7<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715360: sends(8) nullUD g1UD g52UD 0x02080017 0x00000100
2022-07-27 22:49:44.715368: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.715377: sends(8) nullUD g1UD g16UD 0x02080047 0x00000200
2022-07-27 22:49:44.715385: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.715393: mov(8) g122<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715400: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.715409: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.715419: END B0
2022-07-27 22:49:44.715428: NIR (SSA form) for fragment shader:
2022-07-27 22:49:44.715437: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.715446: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.715454: name: TTN
2022-07-27 22:49:44.715463: inputs: 2
2022-07-27 22:49:44.715470: outputs: 1
2022-07-27 22:49:44.715479: uniforms: 0
2022-07-27 22:49:44.715488: ubos: 1
2022-07-27 22:49:44.715497: shared: 0
2022-07-27 22:49:44.715506: ray queries: 0
2022-07-27 22:49:44.715514: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.715524: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.715534: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.715543: decl_var uniform INTERP_MODE_NONE vec4 uniform_21 (21, 21, 0)
2022-07-27 22:49:44.715553: decl_var ubo INTERP_MODE_NONE vec4[22] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.715563: decl_function main (0 params)
2022-07-27 22:49:44.715580: impl main {
2022-07-27 22:49:44.715589: block block_0:
2022-07-27 22:49:44.715599: /* preds: */
2022-07-27 22:49:44.715608: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.715617: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.715627: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.715637: vec4 32 div ssa_3 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=48, component=0, dest_type=float32 /*160*/, io location=48 slots=1 /*176*/) /* in_1 */
2022-07-27 22:49:44.715646: vec1 32 con ssa_4 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.715702: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.715716: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.715726: vec1 32 div ssa_7 = flrp ssa_6.x, ssa_2.x, ssa_3.x
2022-07-27 22:49:44.715736: vec1 32 div ssa_8 = flrp ssa_6.y, ssa_2.y, ssa_3.x
2022-07-27 22:49:44.715745: vec1 32 div ssa_9 = flrp ssa_6.z, ssa_2.z, ssa_3.x
2022-07-27 22:49:44.715755: vec4 32 div ssa_10 = vec4 ssa_7, ssa_8, ssa_9, ssa_2.w
2022-07-27 22:49:44.715763: intrinsic store_output (ssa_10, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.715773: /* succs: block_1 */
2022-07-27 22:49:44.715783: block block_1:
2022-07-27 22:49:44.715791: }
2022-07-27 22:49:44.715799: NIR (final form) for fragment shader:
2022-07-27 22:49:44.715807: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.715815: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.715824: name: TTN
2022-07-27 22:49:44.715833: inputs: 2
2022-07-27 22:49:44.715842: outputs: 1
2022-07-27 22:49:44.715851: uniforms: 0
2022-07-27 22:49:44.715859: ubos: 1
2022-07-27 22:49:44.715869: shared: 0
2022-07-27 22:49:44.715877: ray queries: 0
2022-07-27 22:49:44.715912: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.715922: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.715931: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.715939: decl_var uniform INTERP_MODE_NONE vec4 uniform_21 (21, 21, 0)
2022-07-27 22:49:44.715948: decl_var ubo INTERP_MODE_NONE vec4[22] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.715957: decl_function main (0 params)
2022-07-27 22:49:44.715966: impl main {
2022-07-27 22:49:44.715974: block block_0:
2022-07-27 22:49:44.715983: /* preds: */
2022-07-27 22:49:44.715991: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.716000: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.716009: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.716018: vec4 32 div ssa_3 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=48, component=0, dest_type=float32 /*160*/, io location=48 slots=1 /*176*/) /* in_1 */
2022-07-27 22:49:44.716027: vec1 32 con ssa_4 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.716036: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.716045: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.716053: vec1 32 div ssa_7 = flrp ssa_6.x, ssa_2.x, ssa_3.x
2022-07-27 22:49:44.716062: vec1 32 div ssa_8 = flrp ssa_6.y, ssa_2.y, ssa_3.x
2022-07-27 22:49:44.716079: vec1 32 div ssa_9 = flrp ssa_6.z, ssa_2.z, ssa_3.x
2022-07-27 22:49:44.716088: vec4 32 div ssa_10 = vec4 ssa_7, ssa_8, ssa_9, ssa_2.w
2022-07-27 22:49:44.716096: intrinsic store_output (ssa_10, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.716106: /* succs: block_1 */
2022-07-27 22:49:44.716114: block block_1:
2022-07-27 22:49:44.716123: }
2022-07-27 22:49:44.716131: Native code for unnamed fragment shader TTN (sha1 b1f8d995d2d32a1c0ec7911c237f4d1ca4bbf163)
2022-07-27 22:49:44.716161: SIMD8 shader: 9 instructions. 0 loops. 58 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 144 to 112 bytes (22%)
2022-07-27 22:49:44.716170: START B0 (58 cycles)
2022-07-27 22:49:44.716178: pln(8) g11<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716188: pln(8) g9<1>F g5.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716196: pln(8) g13<1>F g6<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716206: pln(8) g126<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716215: pln(8) g8<1>F g7<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716223: lrp(8) g123<1>F g8<4,4,1>F g11<4,4,1>F g4.4<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716232: lrp(8) g124<1>F g8<4,4,1>F g9<4,4,1>F g4.5<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716240: lrp(8) g125<1>F g8<4,4,1>F g13<4,4,1>F g4.6<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716249: sendc(8) null<1>UW g123<0,1,0>UD 0x88031400
2022-07-27 22:49:44.716257: render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.716266: END B0
2022-07-27 22:49:44.716306: Native code for unnamed fragment shader TTN (sha1 19443fec2f6c2cd45fa7bb5453e75244bc717290)
2022-07-27 22:49:44.716316: SIMD16 shader: 9 instructions. 0 loops. 96 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 144 to 112 bytes (22%)
2022-07-27 22:49:44.716325: START B0 (96 cycles)
2022-07-27 22:49:44.716335: pln(16) g10<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716344: pln(16) g12<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716352: pln(16) g14<1>F g8<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716361: pln(16) g125<1>F g8.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716370: pln(16) g16<1>F g9<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716379: lrp(16) g119<1>F g16<4,4,1>F g10<4,4,1>F g6.4<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716387: lrp(16) g121<1>F g16<4,4,1>F g12<4,4,1>F g6.5<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716397: lrp(16) g123<1>F g16<4,4,1>F g14<4,4,1>F g6.6<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716405: sendc(16) null<1>UW g119<0,1,0>UD 0x90031000
2022-07-27 22:49:44.716414: render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
2022-07-27 22:49:44.716422: END B0
2022-07-27 22:49:44.716431: NIR (SSA form) for vertex shader:
2022-07-27 22:49:44.716440: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.716449: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.716458: name: TTN
2022-07-27 22:49:44.716467: inputs: 3
2022-07-27 22:49:44.716483: outputs: 4
2022-07-27 22:49:44.716491: uniforms: 0
2022-07-27 22:49:44.716500: ubos: 1
2022-07-27 22:49:44.716508: shared: 0
2022-07-27 22:49:44.716516: ray queries: 0
2022-07-27 22:49:44.716525: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.716534: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.716543: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.716552: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.716561: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.716570: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.716580: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.716589: decl_var uniform INTERP_MODE_NONE vec4[8] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.716598: decl_var uniform INTERP_MODE_NONE vec4 uniform_28 (28, 28, 0)
2022-07-27 22:49:44.716607: decl_var ubo INTERP_MODE_NONE vec4[29] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:44.716616: decl_function main (0 params)
2022-07-27 22:49:44.716625: impl main {
2022-07-27 22:49:44.716635: block block_0:
2022-07-27 22:49:44.716643: /* preds: */
2022-07-27 22:49:44.716652: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.716661: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.716670: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.716680: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:44.716690: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:44.716699: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:44.716708: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.716717: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.716726: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.716736: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.716744: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.716753: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.716762: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.716769: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.716777: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.716784: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.716792: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.716800: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.716808: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.716816: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.716824: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.716831: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.716839: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.716846: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.716853: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.716860: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.716867: vec1 32 con ssa_26 = load_const (0x00000040 = 0.000000)
2022-07-27 22:49:44.716881: vec4 32 con ssa_27 = intrinsic load_ubo (ssa_1, ssa_26) (access=0, align_mul=1073741824, align_offset=64, range_base=64, range=16)
2022-07-27 22:49:44.716891: vec1 32 div ssa_28 = fmul ssa_2.x, ssa_27.z
2022-07-27 22:49:44.716900: vec1 32 con ssa_29 = load_const (0x00000050 = 0.000000)
2022-07-27 22:49:44.716909: vec4 32 con ssa_30 = intrinsic load_ubo (ssa_1, ssa_29) (access=0, align_mul=1073741824, align_offset=80, range_base=80, range=16)
2022-07-27 22:49:44.716918: vec1 32 div ssa_31 = ffma ssa_2.y, ssa_30.z, ssa_28
2022-07-27 22:49:44.716927: vec1 32 con ssa_32 = load_const (0x00000060 = 0.000000)
2022-07-27 22:49:44.716936: vec4 32 con ssa_33 = intrinsic load_ubo (ssa_1, ssa_32) (access=0, align_mul=1073741824, align_offset=96, range_base=96, range=16)
2022-07-27 22:49:44.716945: vec1 32 div ssa_34 = ffma ssa_2.z, ssa_33.z, ssa_31
2022-07-27 22:49:44.716953: vec1 32 con ssa_35 = load_const (0x00000070 = 0.000000)
2022-07-27 22:49:44.716960: vec4 32 con ssa_36 = intrinsic load_ubo (ssa_1, ssa_35) (access=0, align_mul=1073741824, align_offset=112, range_base=112, range=16)
2022-07-27 22:49:44.716969: vec1 32 div ssa_37 = ffma ssa_2.w, ssa_36.z, ssa_34
2022-07-27 22:49:44.716977: vec4 32 div ssa_38 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.716985: vec1 32 div ssa_39 = fsat ssa_38.x
2022-07-27 22:49:44.716994: vec1 32 div ssa_40 = fsat ssa_38.y
2022-07-27 22:49:44.717002: vec1 32 div ssa_41 = fsat ssa_38.z
2022-07-27 22:49:44.717009: vec1 32 div ssa_42 = fsat ssa_38.w
2022-07-27 22:49:44.717018: vec4 32 div ssa_43 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.717027: vec1 32 div ssa_44 = fsat ssa_43.x
2022-07-27 22:49:44.717035: vec1 32 div ssa_45 = fsat ssa_43.y
2022-07-27 22:49:44.717043: vec1 32 div ssa_46 = fsat ssa_43.z
2022-07-27 22:49:44.717051: vec1 32 div ssa_47 = fsat ssa_43.w
2022-07-27 22:49:44.717059: vec1 32 div ssa_48 = fabs ssa_37
2022-07-27 22:49:44.717067: vec1 32 con ssa_49 = load_const (0x000001c0 = 0.000000)
2022-07-27 22:49:44.717075: vec4 32 con ssa_50 = intrinsic load_ubo (ssa_1, ssa_49) (access=0, align_mul=1073741824, align_offset=448, range_base=448, range=16)
2022-07-27 22:49:44.717083: vec1 32 div ssa_51 = fneg ssa_48
2022-07-27 22:49:44.717092: vec1 32 div ssa_52 = fadd ssa_50.x, ssa_51
2022-07-27 22:49:44.717100: vec1 32 div ssa_53 = fmul ssa_52, ssa_50.y
2022-07-27 22:49:44.717109: vec1 32 div ssa_54 = fsat ssa_53
2022-07-27 22:49:44.717117: vec4 32 div ssa_55 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.717126: intrinsic store_output (ssa_55, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.717135: vec4 32 div ssa_56 = vec4 ssa_39, ssa_40, ssa_41, ssa_42
2022-07-27 22:49:44.717143: intrinsic store_output (ssa_56, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.717152: vec4 32 div ssa_57 = vec4 ssa_44, ssa_45, ssa_46, ssa_47
2022-07-27 22:49:44.717160: intrinsic store_output (ssa_57, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.717169: vec4 32 div ssa_58 = vec4 ssa_54, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.717177: intrinsic store_output (ssa_58, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.717185: /* succs: block_1 */
2022-07-27 22:49:44.717194: block block_1:
2022-07-27 22:49:44.717203: }
2022-07-27 22:49:44.717243: NIR (final form) for vertex shader:
2022-07-27 22:49:44.717252: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.717260: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.717269: name: TTN
2022-07-27 22:49:44.717278: inputs: 3
2022-07-27 22:49:44.717286: outputs: 4
2022-07-27 22:49:44.717295: uniforms: 0
2022-07-27 22:49:44.717303: ubos: 1
2022-07-27 22:49:44.717311: shared: 0
2022-07-27 22:49:44.717319: ray queries: 0
2022-07-27 22:49:44.717327: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.717335: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.717343: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.717351: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.717359: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.717367: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.717375: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.717383: decl_var uniform INTERP_MODE_NONE vec4[8] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.717391: decl_var uniform INTERP_MODE_NONE vec4 uniform_28 (28, 28, 0)
2022-07-27 22:49:44.717399: decl_var ubo INTERP_MODE_NONE vec4[29] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:44.717407: decl_function main (0 params)
2022-07-27 22:49:44.717414: impl main {
2022-07-27 22:49:44.717422: block block_0:
2022-07-27 22:49:44.717430: /* preds: */
2022-07-27 22:49:44.717437: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.717445: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.717453: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.717461: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:44.717468: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:44.717477: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:44.717484: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.717492: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.717500: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.717507: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.717515: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.717523: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.717531: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.717539: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.717546: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.717554: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.717562: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.717569: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.717576: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.717584: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.717592: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.717600: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.717608: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.717655: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.717664: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.717671: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.717678: vec1 32 con ssa_26 = load_const (0x00000040 = 0.000000)
2022-07-27 22:49:44.717685: vec4 32 con ssa_27 = intrinsic load_ubo (ssa_1, ssa_26) (access=0, align_mul=1073741824, align_offset=64, range_base=64, range=16)
2022-07-27 22:49:44.717692: vec1 32 div ssa_28 = fmul ssa_2.x, ssa_27.z
2022-07-27 22:49:44.717699: vec1 32 con ssa_29 = load_const (0x00000050 = 0.000000)
2022-07-27 22:49:44.717705: vec4 32 con ssa_30 = intrinsic load_ubo (ssa_1, ssa_29) (access=0, align_mul=1073741824, align_offset=80, range_base=80, range=16)
2022-07-27 22:49:44.717713: vec1 32 div ssa_31 = ffma ssa_2.y, ssa_30.z, ssa_28
2022-07-27 22:49:44.717720: vec1 32 con ssa_32 = load_const (0x00000060 = 0.000000)
2022-07-27 22:49:44.717728: vec4 32 con ssa_33 = intrinsic load_ubo (ssa_1, ssa_32) (access=0, align_mul=1073741824, align_offset=96, range_base=96, range=16)
2022-07-27 22:49:44.717735: vec1 32 div ssa_34 = ffma ssa_2.z, ssa_33.z, ssa_31
2022-07-27 22:49:44.717742: vec1 32 con ssa_35 = load_const (0x00000070 = 0.000000)
2022-07-27 22:49:44.717749: vec4 32 con ssa_36 = intrinsic load_ubo (ssa_1, ssa_35) (access=0, align_mul=1073741824, align_offset=112, range_base=112, range=16)
2022-07-27 22:49:44.717757: vec1 32 div ssa_37 = ffma ssa_2.w, ssa_36.z, ssa_34
2022-07-27 22:49:44.717764: vec4 32 div ssa_38 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.717772: vec1 32 div ssa_39 = fsat ssa_38.x
2022-07-27 22:49:44.717779: vec1 32 div ssa_40 = fsat ssa_38.y
2022-07-27 22:49:44.717786: vec1 32 div ssa_41 = fsat ssa_38.z
2022-07-27 22:49:44.717793: vec1 32 div ssa_42 = fsat ssa_38.w
2022-07-27 22:49:44.717800: vec4 32 div ssa_43 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.717807: vec1 32 div ssa_44 = fsat ssa_43.x
2022-07-27 22:49:44.717815: vec1 32 div ssa_45 = fsat ssa_43.y
2022-07-27 22:49:44.717822: vec1 32 div ssa_46 = fsat ssa_43.z
2022-07-27 22:49:44.717828: vec1 32 div ssa_47 = fsat ssa_43.w
2022-07-27 22:49:44.717835: vec1 32 div ssa_48 = fabs ssa_37
2022-07-27 22:49:44.717842: vec1 32 con ssa_49 = load_const (0x000001c0 = 0.000000)
2022-07-27 22:49:44.717850: vec4 32 con ssa_50 = intrinsic load_ubo (ssa_1, ssa_49) (access=0, align_mul=1073741824, align_offset=448, range_base=448, range=16)
2022-07-27 22:49:44.717858: vec1 32 div ssa_51 = fneg ssa_48
2022-07-27 22:49:44.717865: vec1 32 div ssa_52 = fadd ssa_50.x, ssa_51
2022-07-27 22:49:44.717873: vec1 32 div ssa_53 = fmul ssa_52, ssa_50.y
2022-07-27 22:49:44.717881: vec1 32 div ssa_54 = fsat ssa_53
2022-07-27 22:49:44.717888: vec4 32 div ssa_55 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.717895: intrinsic store_output (ssa_55, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.717905: vec4 32 div ssa_56 = vec4 ssa_39, ssa_40, ssa_41, ssa_42
2022-07-27 22:49:44.717913: intrinsic store_output (ssa_56, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.717920: vec4 32 div ssa_57 = vec4 ssa_44, ssa_45, ssa_46, ssa_47
2022-07-27 22:49:44.717929: intrinsic store_output (ssa_57, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.717937: vec4 32 div ssa_58 = vec4 ssa_54, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.717944: intrinsic store_output (ssa_58, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.717987: /* succs: block_1 */
2022-07-27 22:49:44.717997: block block_1:
2022-07-27 22:49:44.718004: }
2022-07-27 22:49:44.718011: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.718018: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.718025: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.718033: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.718040: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.718047: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.718054: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.718061: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718067: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718075: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718084: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718092: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718100: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718106: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718113: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718120: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718128: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718135: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718143: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718150: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718158: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718166: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718173: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718180: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.718187: Native code for unnamed vertex shader TTN (sha1 447eb0bb1111eb6ee202eb90e872aa08ec4e3291)
2022-07-27 22:49:44.718194: SIMD8 shader: 34 instructions. 0 loops. 130 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 544 to 432 bytes (21%)
2022-07-27 22:49:44.718202: START B0 (130 cycles)
2022-07-27 22:49:44.718210: mul(8) g27<1>F g7<8,8,1>F g2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718218: mul(8) g28<1>F g7<8,8,1>F g2.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718225: mul(8) g29<1>F g7<8,8,1>F g2.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718233: mul(8) g30<1>F g7<8,8,1>F g2.3<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718241: mul(8) g43<1>F g7<8,8,1>F g4.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718248: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718255: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718262: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718270: mov.sat(8) g22<1>F g14<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718278: mov.sat(8) g23<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718287: mov.sat(8) g24<1>F g16<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718295: mov.sat(8) g25<1>F g17<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718304: mov.sat(8) g26<1>F g18<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718312: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.718321: mad(8) g31<1>F g27<4,4,1>F g2.4<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718329: mad(8) g32<1>F g28<4,4,1>F g2.5<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718338: mad(8) g33<1>F g29<4,4,1>F g2.6<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718354: mad(8) g34<1>F g30<4,4,1>F g2.7<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718364: mad(8) g44<1>F g43<4,4,1>F g4.6<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718373: mad(8) g35<1>F g31<4,4,1>F g3.0<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718381: mad(8) g36<1>F g32<4,4,1>F g3.1<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718388: mad(8) g37<1>F g33<4,4,1>F g3.2<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718397: mad(8) g38<1>F g34<4,4,1>F g3.3<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718406: mad(8) g45<1>F g44<4,4,1>F g5.2<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718415: mad(8) g60<1>F g35<4,4,1>F g3.4<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718424: mad(8) g61<1>F g36<4,4,1>F g3.5<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718433: mad(8) g62<1>F g37<4,4,1>F g3.6<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718441: mad(8) g63<1>F g38<4,4,1>F g3.7<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718450: mad(8) g46<1>F g45<4,4,1>F g5.6<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718458: add(8) g55<1>F g6<0,1,0>F -(abs)g46<8,8,1>F { align1 1Q };
2022-07-27 22:49:44.718466: mul.sat(8) g122<1>F g55<8,8,1>F g6.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718474: sends(8) nullUD g1UD g60UD 0x02080017 0x00000100
2022-07-27 22:49:44.718482: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.718491: sends(8) nullUD g1UD g19UD 0x02080047 0x00000200
2022-07-27 22:49:44.718500: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.718507: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.718516: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.718524: END B0
2022-07-27 22:49:44.718533: NIR (SSA form) for vertex shader:
2022-07-27 22:49:44.718540: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.718549: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.718558: name: TTN
2022-07-27 22:49:44.718568: inputs: 3
2022-07-27 22:49:44.718576: outputs: 4
2022-07-27 22:49:44.718585: uniforms: 0
2022-07-27 22:49:44.718593: shared: 0
2022-07-27 22:49:44.718601: ray queries: 0
2022-07-27 22:49:44.718609: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.718618: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.718626: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.718634: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.718641: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.718649: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.718657: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.718665: decl_function main (0 params)
2022-07-27 22:49:44.718674: impl main {
2022-07-27 22:49:44.718683: block block_0:
2022-07-27 22:49:44.718691: /* preds: */
2022-07-27 22:49:44.718724: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.718735: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.718743: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.718752: vec4 32 div ssa_3 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.718761: vec1 32 div ssa_4 = fsat ssa_3.x
2022-07-27 22:49:44.718768: vec1 32 div ssa_5 = fsat ssa_3.y
2022-07-27 22:49:44.718776: vec1 32 div ssa_6 = fsat ssa_3.z
2022-07-27 22:49:44.718783: vec1 32 div ssa_7 = fsat ssa_3.w
2022-07-27 22:49:44.718790: vec4 32 div ssa_8 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.718798: vec1 32 div ssa_9 = fsat ssa_8.x
2022-07-27 22:49:44.718805: vec1 32 div ssa_10 = fsat ssa_8.y
2022-07-27 22:49:44.718812: vec1 32 div ssa_11 = fsat ssa_8.z
2022-07-27 22:49:44.718819: vec1 32 div ssa_12 = fsat ssa_8.w
2022-07-27 22:49:44.718826: intrinsic store_output (ssa_2, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.718834: vec4 32 div ssa_13 = vec4 ssa_4, ssa_5, ssa_6, ssa_7
2022-07-27 22:49:44.718841: intrinsic store_output (ssa_13, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.718848: vec4 32 div ssa_14 = vec4 ssa_9, ssa_10, ssa_11, ssa_12
2022-07-27 22:49:44.718855: intrinsic store_output (ssa_14, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.718862: vec4 32 div ssa_15 = vec4 ssa_8.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.718869: intrinsic store_output (ssa_15, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.718876: /* succs: block_1 */
2022-07-27 22:49:44.718884: block block_1:
2022-07-27 22:49:44.718891: }
2022-07-27 22:49:44.718900: NIR (final form) for vertex shader:
2022-07-27 22:49:44.718908: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.718916: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.718925: name: TTN
2022-07-27 22:49:44.718933: inputs: 3
2022-07-27 22:49:44.718941: outputs: 4
2022-07-27 22:49:44.718949: uniforms: 0
2022-07-27 22:49:44.718958: shared: 0
2022-07-27 22:49:44.718966: ray queries: 0
2022-07-27 22:49:44.718974: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.718983: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.718991: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.718999: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.719007: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.719015: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.719024: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.719032: decl_function main (0 params)
2022-07-27 22:49:44.719041: impl main {
2022-07-27 22:49:44.719049: block block_0:
2022-07-27 22:49:44.719057: /* preds: */
2022-07-27 22:49:44.719065: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.719074: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.719081: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.719098: vec4 32 div ssa_3 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.719106: vec1 32 div ssa_4 = fsat ssa_3.x
2022-07-27 22:49:44.719114: vec1 32 div ssa_5 = fsat ssa_3.y
2022-07-27 22:49:44.719123: vec1 32 div ssa_6 = fsat ssa_3.z
2022-07-27 22:49:44.719130: vec1 32 div ssa_7 = fsat ssa_3.w
2022-07-27 22:49:44.719138: vec4 32 div ssa_8 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.719146: vec1 32 div ssa_9 = fsat ssa_8.x
2022-07-27 22:49:44.719154: vec1 32 div ssa_10 = fsat ssa_8.y
2022-07-27 22:49:44.719162: vec1 32 div ssa_11 = fsat ssa_8.z
2022-07-27 22:49:44.719171: vec1 32 div ssa_12 = fsat ssa_8.w
2022-07-27 22:49:44.719200: intrinsic store_output (ssa_2, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.719211: vec4 32 div ssa_13 = vec4 ssa_4, ssa_5, ssa_6, ssa_7
2022-07-27 22:49:44.719220: intrinsic store_output (ssa_13, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.719229: vec4 32 div ssa_14 = vec4 ssa_9, ssa_10, ssa_11, ssa_12
2022-07-27 22:49:44.719237: intrinsic store_output (ssa_14, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.719245: vec4 32 div ssa_15 = vec4 ssa_8.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.719254: intrinsic store_output (ssa_15, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.719263: /* succs: block_1 */
2022-07-27 22:49:44.719271: block block_1:
2022-07-27 22:49:44.719279: }
2022-07-27 22:49:44.719288: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.719297: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.719306: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.719315: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.719323: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.719331: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.719339: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.719348: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719356: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719364: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719373: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719382: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719390: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719399: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719408: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719416: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719425: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719433: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719442: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719450: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719458: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719466: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719474: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719483: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.719491: Native code for unnamed vertex shader TTN (sha1 ffb696f9ce71a921f6078357aeddcf510fa5d013)
2022-07-27 22:49:44.719500: SIMD8 shader: 17 instructions. 0 loops. 80 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 272 to 160 bytes (41%)
2022-07-27 22:49:44.719508: START B0 (80 cycles)
2022-07-27 22:49:44.719517: mov.sat(8) g14<1>F g6<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719548: mov.sat(8) g15<1>F g7<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719558: mov.sat(8) g16<1>F g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719566: mov.sat(8) g17<1>F g9<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719574: mov.sat(8) g18<1>F g10<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719582: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719590: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719597: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719604: mov(8) g27<1>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719612: mov(8) g28<1>F g3<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719621: mov(8) g29<1>F g4<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719629: mov(8) g30<1>F g5<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719637: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.719646: sends(8) nullUD g1UD g27UD 0x02080017 0x00000100
2022-07-27 22:49:44.719654: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.719663: sends(8) nullUD g1UD g14UD 0x02080047 0x00000200
2022-07-27 22:49:44.719670: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.719679: mov(8) g122<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719686: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.719694: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.719703: END B0
2022-07-27 22:49:44.719711: NIR (SSA form) for fragment shader:
2022-07-27 22:49:44.719719: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.719727: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.719735: name: TTN
2022-07-27 22:49:44.719743: inputs: 1
2022-07-27 22:49:44.719752: outputs: 1
2022-07-27 22:49:44.719760: uniforms: 0
2022-07-27 22:49:44.719768: ubos: 1
2022-07-27 22:49:44.719776: shared: 0
2022-07-27 22:49:44.719785: ray queries: 0
2022-07-27 22:49:44.719793: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.719801: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.719809: decl_var uniform INTERP_MODE_NONE vec4[2] uniform_21 (21, 21, 0)
2022-07-27 22:49:44.719818: decl_var ubo INTERP_MODE_NONE vec4[23] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.719826: decl_function main (0 params)
2022-07-27 22:49:44.719835: impl main {
2022-07-27 22:49:44.719843: block block_0:
2022-07-27 22:49:44.719851: /* preds: */
2022-07-27 22:49:44.719860: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.719868: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.719877: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.719886: vec4 32 div ssa_3 = intrinsic load_frag_coord () ()
2022-07-27 22:49:44.719908: vec1 32 con ssa_4 = load_const (0x00000160 = 0.000000)
2022-07-27 22:49:44.719918: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.719926: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=352, range_base=352, range=16)
2022-07-27 22:49:44.719935: vec1 32 div ssa_7 = fneg ssa_3.z
2022-07-27 22:49:44.719943: vec1 32 div ssa_8 = fadd ssa_6.x, ssa_7
2022-07-27 22:49:44.719951: vec1 32 div ssa_9 = fmul ssa_8, ssa_6.y
2022-07-27 22:49:44.719959: vec1 32 div ssa_10 = fsat ssa_9
2022-07-27 22:49:44.719966: vec1 32 con ssa_11 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.719974: vec4 32 con ssa_12 = intrinsic load_ubo (ssa_5, ssa_11) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.719982: vec1 32 div ssa_13 = flrp ssa_12.x, ssa_2.x, ssa_10
2022-07-27 22:49:44.719990: vec1 32 div ssa_14 = flrp ssa_12.y, ssa_2.y, ssa_10
2022-07-27 22:49:44.719998: vec1 32 div ssa_15 = flrp ssa_12.z, ssa_2.z, ssa_10
2022-07-27 22:49:44.720006: vec4 32 div ssa_16 = vec4 ssa_13, ssa_14, ssa_15, ssa_2.w
2022-07-27 22:49:44.720014: intrinsic store_output (ssa_16, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.720022: /* succs: block_1 */
2022-07-27 22:49:44.720031: block block_1:
2022-07-27 22:49:44.720039: }
2022-07-27 22:49:44.720047: NIR (final form) for fragment shader:
2022-07-27 22:49:44.720056: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.720064: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.720073: name: TTN
2022-07-27 22:49:44.720082: inputs: 1
2022-07-27 22:49:44.720090: outputs: 1
2022-07-27 22:49:44.720099: uniforms: 0
2022-07-27 22:49:44.720107: ubos: 1
2022-07-27 22:49:44.720115: shared: 0
2022-07-27 22:49:44.720123: ray queries: 0
2022-07-27 22:49:44.720132: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.720140: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.720149: decl_var uniform INTERP_MODE_NONE vec4[2] uniform_21 (21, 21, 0)
2022-07-27 22:49:44.720157: decl_var ubo INTERP_MODE_NONE vec4[23] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.720166: decl_function main (0 params)
2022-07-27 22:49:44.720174: impl main {
2022-07-27 22:49:44.720183: block block_0:
2022-07-27 22:49:44.720192: /* preds: */
2022-07-27 22:49:44.720200: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.720208: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.720217: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.720224: vec4 32 div ssa_3 = intrinsic load_frag_coord () ()
2022-07-27 22:49:44.720232: vec1 32 con ssa_4 = load_const (0x00000160 = 0.000000)
2022-07-27 22:49:44.720240: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.720248: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=352, range_base=352, range=16)
2022-07-27 22:49:44.720257: vec1 32 div ssa_7 = fneg ssa_3.z
2022-07-27 22:49:44.720265: vec1 32 div ssa_8 = fadd ssa_6.x, ssa_7
2022-07-27 22:49:44.720288: vec1 32 div ssa_9 = fmul ssa_8, ssa_6.y
2022-07-27 22:49:44.720296: vec1 32 div ssa_10 = fsat ssa_9
2022-07-27 22:49:44.720304: vec1 32 con ssa_11 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.720312: vec4 32 con ssa_12 = intrinsic load_ubo (ssa_5, ssa_11) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.720319: vec1 32 div ssa_13 = flrp ssa_12.x, ssa_2.x, ssa_10
2022-07-27 22:49:44.720350: vec1 32 div ssa_14 = flrp ssa_12.y, ssa_2.y, ssa_10
2022-07-27 22:49:44.720360: vec1 32 div ssa_15 = flrp ssa_12.z, ssa_2.z, ssa_10
2022-07-27 22:49:44.720368: vec4 32 div ssa_16 = vec4 ssa_13, ssa_14, ssa_15, ssa_2.w
2022-07-27 22:49:44.720376: intrinsic store_output (ssa_16, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.720384: /* succs: block_1 */
2022-07-27 22:49:44.720393: block block_1:
2022-07-27 22:49:44.720401: }
2022-07-27 22:49:44.720410: Native code for unnamed fragment shader TTN (sha1 79cb4fc7ba74b8716c799ae02334d0968987c41c)
2022-07-27 22:49:44.720418: SIMD8 shader: 11 instructions. 0 loops. 74 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 176 to 128 bytes (27%)
2022-07-27 22:49:44.720427: START B0 (74 cycles)
2022-07-27 22:49:44.720435: pln(8) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720443: pln(8) g9<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720452: pln(8) g13<1>F g7<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720461: pln(8) g126<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720470: mov(8) g8<1>F null<8,8,1>F { align1 1Q };
2022-07-27 22:49:44.720478: ERROR: src0 is null
2022-07-27 22:49:44.720487: add(8) g2<1>F g5<0,1,0>F -g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720496: mul.sat(8) g3<1>F g2<8,8,1>F g5.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.720505: lrp(8) g123<1>F g3<4,4,1>F g11<4,4,1>F g4.4<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720513: lrp(8) g124<1>F g3<4,4,1>F g9<4,4,1>F g4.5<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720521: lrp(8) g125<1>F g3<4,4,1>F g13<4,4,1>F g4.6<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720530: sendc(8) null<1>UW g123<0,1,0>UD 0x88031400
2022-07-27 22:49:44.720539: render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.720547: END B0
2022-07-27 22:49:44.720555: NineTests: ../src/intel/compiler/brw_fs_generator.cpp:2620: int fs_generator::generate_code(const cfg_t*, int, shader_stats, const brw::performance&, brw_compile_stats*): Assertion `validated' failed.
2022-07-27 22:49:44.720565: ./NineTests.sh: line 3: 293 Aborted INTEL_DEBUG=shaders ./NineTests