r300g: Vertex register allocation broken
The liveness is broken. Take:
Vertex Program: after 'dataflow optimize'
# Radeon Compiler Program
0: MOV temp[4].x, input[1].x___;
1: MOV temp[5].x, none.0___;
2: BGNLOOP;
3: SGE temp[6].x, temp[5].x___, const[0].x___;
4: IF temp[6].x___;
5: BRK;
6: ENDIF;
7: SEQ temp[7], temp[5].xxxx, const[1].01zw;
8: SLT temp[10].x, -temp[7].x___, none.0___;
9: MAD temp[11].x, -temp[10].x___, temp[3].x___, temp[3].x___;
10: MAD temp[3].x, temp[10].x___, temp[4].x___, temp[11].x___;
11: SLT temp[12].x, -temp[7].y___, none.0___;
12: MAD temp[13].x, -temp[12].x___, temp[2].x___, temp[2].x___;
13: MAD temp[2].x, temp[12].x___, temp[4].x___, temp[13].x___;
14: SLT temp[14].x, -temp[7].z___, none.0___;
15: MAD temp[15].x, -temp[14].x___, temp[1].x___, temp[1].x___;
16: MAD temp[1].x, temp[14].x___, temp[4].x___, temp[15].x___;
17: SLT temp[16].x, -temp[7].w___, none.0___;
18: MAD temp[17].x, -temp[16].x___, temp[0].x___, temp[0].x___;
19: MAD temp[0].x, temp[16].x___, temp[4].x___, temp[17].x___;
20: MUL temp[4].x, temp[4].x___, const[2].x___;
21: ADD temp[5].x, temp[5].x___, none.1___;
22: ENDLOOP;
23: ADD temp[7].x, temp[3].x___, temp[2].x___;
24: ADD temp[8].x, temp[7].x___, temp[1].x___;
25: ADD output[1].x, temp[8].x___, temp[0].x___;
26: MOV output[1].yzw, none._001;
27: MOV output[0], input[0];
28: MOV output[2], input[0];
temp 0 only gets allocated at instr 19, while it actually needed to be allocated at instr 2 -- the temps all get allocated on top of each other instead of being live across the loop. Need to take the live reg dataflow stuff from nir_to_tgsi and port it over to fix a giant pile of dEQPs.