intel/fs: regression on MTL with 64bit values in UBO
A few tests are asserting in the validator :
./bin/arb_gpu_shader_fp64-fs-non-uniform-control-flow-ubo -auto -fbo
Native code for unnamed fragment shader GLSL3 (src_hash 0xd3dfcd7f) (sha1 e6925174477637b518237da46feec1f919fe2bf5)
SIMD8 shader: 35 instructions. 0 loops. 220 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 560 to 464 bytes (17%)
START B0 (220 cycles)
add(16) g6<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H };
add(16) g7<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H };
mov(8) g123<1>F 0x0F /* 0F */ { align1 1Q compacted };
mov(8) g124<1>F 0x3f800000F /* 1F */ { align1 1Q compacted };
sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 };
mov(8) g2<1>F g6<16,8,2>UW { align1 1Q };
sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 };
mov(8) g18<1>F g7<16,8,2>UW { align1 1Q };
add(8) g11<1>F g2<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1Q F@2 compacted };
add(8) g12<1>F g18<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1Q F@2 compacted };
mov(8) g14<1>D g11<1,1,0>F { align1 1Q F@2 compacted };
mad(8) g13<1>F g5.1<0,1,0>F g5.0<0,1,0>F g12<1,1,1>F { align1 1Q F@1 compacted };
mul(8) acc0<1>D g14<8,8,1>D 0x0843UW { align1 1Q I@1 };
mov(8) g19<1>D g13<1,1,0>F { align1 1Q F@1 compacted };
mach(8) g15<1>D g14<8,8,1>D -2078209981D { align1 1Q AccWrEnable };
add(8) g16<1>D g15<1,1,0>D g14<1,1,0>D { align1 1Q I@1 compacted };
mul(8) acc0<1>D g19<8,8,1>D 0x0843UW { align1 1Q I@3 };
asr(8) g17<1>D g16<8,8,1>D 0x00000004UD { align1 1Q I@2 };
mach(8) g20<1>D g19<8,8,1>D -2078209981D { align1 1Q AccWrEnable };
shr(8) g3<1>UD g17<1,1,0>UD 0x0000001fUD { align1 1Q I@2 compacted };
add(8) g21<1>D g20<1,1,0>D g19<1,1,0>D { align1 1Q I@2 compacted };
asr(8) g22<1>D g21<8,8,1>D 0x00000004UD { align1 1Q I@1 };
shr(8) g23<1>UD g22<1,1,0>UD 0x0000001fUD { align1 1Q I@1 compacted };
add(8) g24<1>D g22<1,1,0>D g23<1,1,0>D { align1 1Q I@1 compacted };
add3(8) g25<1>D g17<8,8,1>D g3<8,8,1>D g24<1,1,1>D { align1 1Q I@1 };
and.z.f0.0(8) null<1>UD g25<8,8,1>UD 0x00000001UD { align1 1Q I@1 };
(+f0.0) sel(8) g10<1>UQ g4.1<0,1,0>UQ g4.3<0,1,0>UQ { align1 1Q };
ERROR: 64-bit int destination, but platform does not support it
ERROR: 64-bit int source, but platform does not support it
(+f0.0) sel(8) g8<1>UQ g4<0,1,0>UQ g4.2<0,1,0>UQ { align1 1Q };
ERROR: 64-bit int destination, but platform does not support it
ERROR: 64-bit int source, but platform does not support it
sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.dst };
mov(8) g28<2>F g10<4,4,1>DF { align1 1Q $0 };
sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst };
mov(8) g26<2>F g8<4,4,1>DF { align1 1Q $1 };
mov(8) g126<1>UD g28<8,4,2>UD { align1 1Q $0.dst };
mov(8) g125<1>UD g26<8,4,2>UD { align1 1Q $1.dst };
sendc(8) nullUD g125UD g123UD 0x04031400 0x00000080
render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 2 ex_mlen 2 rlen 0 { align1 1Q A@1 EOT };
END B0
Bisect to :
commit ea423aba1b45f90526149f1e0c190ce113ffa7b7
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon Mar 18 22:52:35 2024 -0700
intel/brw: Split out 64-bit lowering from algebraic optimizations
Edited by Lionel Landwerlin