src/intel/common/intel_gem.c

@@ -250,3 +250,19 @@ intel_gem_supports_protected_context(int fd)
 
    return ret;
 }
+
+bool
+intel_gem_get_param(int fd, uint32_t param, int *value)
+{
+   drm_i915_getparam_t gp = {
+      .param = param,
+      .value = value,
+   };
+   return intel_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == 0;
+}
+
+bool intel_gem_can_render_on_fd(int fd)
+{
+   int val;
+   return intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, &val) && val > 0;
+}

src/intel/common/intel_gem.h

@@ -174,6 +174,8 @@ intel_gem_get_context_param(int fd, uint32_t context, uint32_t param,
                             uint64_t *value);
 
 bool intel_gem_read_render_timestamp(int fd, uint64_t *value);
+bool intel_gem_get_param(int fd, uint32_t param, int *value);
+bool intel_gem_can_render_on_fd(int fd);
 
 #ifdef __cplusplus
 }

src/intel/common/tests/mi_builder_test.cpp

@@ -30,6 +30,7 @@
 #include "c99_compat.h"
 #include "common/intel_gem.h"
 #include "dev/intel_device_info.h"
+#include "intel_gem.h"
 #include "drm-uapi/i915_drm.h"
 #include "genxml/gen_macros.h"
 #include "util/macros.h"
@@ -189,11 +190,8 @@ mi_builder_test::SetUp()
           * --device option with it.
           */
          int device_id;
-         drm_i915_getparam getparam = drm_i915_getparam();
-         getparam.param = I915_PARAM_CHIPSET_ID;
-         getparam.value = &device_id;
-         ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM,
-                            (void *)&getparam), 0) << strerror(errno);
+         ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, &device_id))
+               << strerror(errno);
 
          ASSERT_TRUE(intel_get_device_info_from_pci_id(device_id, &devinfo));
          if (devinfo.ver != GFX_VER ||
@@ -215,11 +213,8 @@ mi_builder_test::SetUp()
    if (GFX_VER >= 8) {
       /* On gfx8+, we require softpin */
       int has_softpin;
-      drm_i915_getparam getparam = drm_i915_getparam();
-      getparam.param = I915_PARAM_HAS_EXEC_SOFTPIN;
-      getparam.value = &has_softpin;
-      ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM,
-                         (void *)&getparam), 0) << strerror(errno);
+      ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN, &has_softpin))
+            << strerror(errno);
       ASSERT_TRUE(has_softpin);
    }
 

src/intel/compiler/brw_fs.cpp

@@ -3933,15 +3933,147 @@ fs_visitor::lower_load_payload()
    return progress;
 }
 
+/**
+ * Factor an unsigned 32-bit integer.
+ *
+ * Attempts to factor \c x into two values that are at most 0xFFFF.  If no
+ * such factorization is possible, either because the value is too large or is
+ * prime, both \c result_a and \c result_b will be zero.
+ */
+static void
+factor_uint32(uint32_t x, unsigned *result_a, unsigned *result_b)
+{
+   /* This is necessary to prevent various opportunities for division by zero
+    * below.
+    */
+   assert(x > 0xffff);
+
+   /* This represents the actual expected constraints on the input.  Namely,
+    * both the upper and lower words should be > 1.
+    */
+   assert(x >= 0x00020002);
+
+   *result_a = 0;
+   *result_b = 0;
+
+   /* The value is too large to factor with the constraints. */
+   if (x > (0xffffu * 0xffffu))
+      return;
+
+   /* A non-prime number will have the form p*q*d where p is some prime
+    * number, q > 1, and 1 <= d <= q.  To meet the constraints of this
+    * function, (p*d) < 0x10000.  This implies d <= floor(0xffff / p).
+    * Furthermore, since q < 0x10000, d >= floor(x / (0xffff * p)).  Finally,
+    * floor(x / (0xffff * p)) <= d <= floor(0xffff / p).
+    *
+    * The observation is finding the largest possible value of p reduces the
+    * possible range of d.  After selecting p, all values of d in this range
+    * are tested until a factorization is found.  The size of the range of
+    * possible values of d sets an upper bound on the run time of the
+    * function.
+    */
+   static const uint16_t primes[256] = {
+         2,    3,    5,    7,   11,   13,   17,   19,
+        23,   29,   31,   37,   41,   43,   47,   53,
+        59,   61,   67,   71,   73,   79,   83,   89,
+        97,  101,  103,  107,  109,  113,  127,  131,  /*  32 */
+       137,  139,  149,  151,  157,  163,  167,  173,
+       179,  181,  191,  193,  197,  199,  211,  223,
+       227,  229,  233,  239,  241,  251,  257,  263,
+       269,  271,  277,  281,  283,  293,  307,  311,  /*  64 */
+       313,  317,  331,  337,  347,  349,  353,  359,
+       367,  373,  379,  383,  389,  397,  401,  409,
+       419,  421,  431,  433,  439,  443,  449,  457,
+       461,  463,  467,  479,  487,  491,  499,  503,  /*  96 */
+       509,  521,  523,  541,  547,  557,  563,  569,
+       571,  577,  587,  593,  599,  601,  607,  613,
+       617,  619,  631,  641,  643,  647,  653,  659,
+       661,  673,  677,  683,  691,  701,  709,  719,   /* 128 */
+       727,  733,  739,  743,  751,  757,  761,  769,
+       773,  787,  797,  809,  811,  821,  823,  827,
+       829,  839,  853,  857,  859,  863,  877,  881,
+       883,  887,  907,  911,  919,  929,  937,  941,  /* 160 */
+       947,  953,  967,  971,  977,  983,  991,  997,
+      1009, 1013, 1019, 1021, 1031, 1033, 1039, 1049,
+      1051, 1061, 1063, 1069, 1087, 1091, 1093, 1097,
+      1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163,  /* 192 */
+      1171, 1181, 1187, 1193, 1201, 1213, 1217, 1223,
+      1229, 1231, 1237, 1249, 1259, 1277, 1279, 1283,
+      1289, 1291, 1297, 1301, 1303, 1307, 1319, 1321,
+      1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423,  /* 224 */
+      1427, 1429, 1433, 1439, 1447, 1451, 1453, 1459,
+      1471, 1481, 1483, 1487, 1489, 1493, 1499, 1511,
+      1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571,
+      1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619,  /* 256 */
+   };
+
+   unsigned p;
+   unsigned x_div_p;
+
+   for (int i = ARRAY_SIZE(primes) - 1; i >= 0; i--) {
+      p = primes[i];
+      x_div_p = x / p;
+
+      if ((x_div_p * p) == x)
+         break;
+   }
+
+   /* A prime factor was not found. */
+   if (x_div_p * p != x)
+      return;
+
+   /* Terminate early if d=1 is a solution. */
+   if (x_div_p < 0x10000) {
+      *result_a = x_div_p;
+      *result_b = p;
+      return;
+   }
+
+   /* Pick the maximum possible value for 'd'.  It's important that the loop
+    * below execute while d <= max_d because max_d is a valid value.  Having
+    * the wrong loop bound would cause 1627*1367*47 (0x063b0c83) to be
+    * incorrectly reported as not being factorable.  The problem would occur
+    * with any value that is a factor of two primes in the table and one prime
+    * not in the table.
+    */
+   const unsigned max_d = 0xffff / p;
+
+   /* Pick an initial value of 'd' that (combined with rejecting too large
+    * values above) guarantees that 'q' will always be small enough.
+    * DIV_ROUND_UP is used to prevent 'd' from being zero.
+    */
+   for (unsigned d = DIV_ROUND_UP(x_div_p, 0xffff); d <= max_d; d++) {
+      unsigned q = x_div_p / d;
+
+      if ((q * d) == x_div_p) {
+         assert(p * d * q == x);
+         assert((p * d) < 0x10000);
+
+         *result_a = q;
+         *result_b = p * d;
+         break;
+      }
+
+      /* Since every value of 'd' is tried, as soon as 'd' is larger
+       * than 'q', we're just re-testing combinations that have
+       * already been tested.
+       */
+      if (d > q)
+         break;
+   }
+}
+
 void
 fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
 {
    const fs_builder ibld(this, block, inst);
 
-   const bool ud = (inst->src[1].type == BRW_REGISTER_TYPE_UD);
+   /* It is correct to use inst->src[1].d in both end of the comparison.
+    * Using .ud in the UINT16_MAX comparison would cause any negative value to
+    * fail the check.
+    */
    if (inst->src[1].file == IMM &&
-       (( ud && inst->src[1].ud <= UINT16_MAX) ||
-        (!ud && inst->src[1].d <= INT16_MAX && inst->src[1].d >= INT16_MIN))) {
+       (inst->src[1].d >= INT16_MIN && inst->src[1].d <= UINT16_MAX)) {
       /* The MUL instruction isn't commutative. On Gen <= 6, only the low
        * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
        * src1 are used.
@@ -3949,6 +4081,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
        * If multiplying by an immediate value that fits in 16-bits, do a
        * single MUL instruction with that value in the proper location.
        */
+      const bool ud = (inst->src[1].d >= 0);
       if (devinfo->ver < 7) {
          fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);
          ibld.MOV(imm, inst->src[1]);
@@ -4029,6 +4162,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
       high.stride = inst->dst.stride;
       high.offset = inst->dst.offset % REG_SIZE;
 
+      bool do_addition = true;
       if (devinfo->ver >= 7) {
          /* From Wa_1604601757:
           *
@@ -4047,10 +4181,37 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
             lower_src_modifiers(this, block, inst, 1);
 
          if (inst->src[1].file == IMM) {
-            ibld.MUL(low, inst->src[0],
-                     brw_imm_uw(inst->src[1].ud & 0xffff));
-            ibld.MUL(high, inst->src[0],
-                     brw_imm_uw(inst->src[1].ud >> 16));
+            unsigned a;
+            unsigned b;
+
+            /* If the immeditate value can be factored into two values, A and
+             * B, that each fit in 16-bits, the multiplication result can
+             * instead be calculated as (src1 * (A * B)) = ((src1 * A) * B).
+             * This saves an operation (the addition) and a temporary register
+             * (high).
+             *
+             * Skip the optimization if either the high word or the low word
+             * is 0 or 1.  In these conditions, at least one of the
+             * multiplications generated by the straightforward method will be
+             * eliminated anyway.
+             */
+            if (inst->src[1].ud > 0x0001ffff &&
+                (inst->src[1].ud & 0xffff) > 1) {
+               factor_uint32(inst->src[1].ud, &a, &b);
+
+               if (a != 0) {
+                  ibld.MUL(low, inst->src[0], brw_imm_uw(a));
+                  ibld.MUL(low, low, brw_imm_uw(b));
+                  do_addition = false;
+               }
+            }
+
+            if (do_addition) {
+               ibld.MUL(low, inst->src[0],
+                        brw_imm_uw(inst->src[1].ud & 0xffff));
+               ibld.MUL(high, inst->src[0],
+                        brw_imm_uw(inst->src[1].ud >> 16));
+            }
          } else {
             ibld.MUL(low, inst->src[0],
                      subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0));
@@ -4067,9 +4228,11 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
                   inst->src[1]);
       }
 
-      ibld.ADD(subscript(low, BRW_REGISTER_TYPE_UW, 1),
-               subscript(low, BRW_REGISTER_TYPE_UW, 1),
-               subscript(high, BRW_REGISTER_TYPE_UW, 0));
+      if (do_addition) {
+         ibld.ADD(subscript(low, BRW_REGISTER_TYPE_UW, 1),
+                  subscript(low, BRW_REGISTER_TYPE_UW, 1),
+                  subscript(high, BRW_REGISTER_TYPE_UW, 0));
+      }
 
       if (needs_mov || inst->conditional_mod)
          set_condmod(inst->conditional_mod, ibld.MOV(orig_dst, low));

src/intel/compiler/brw_fs_copy_propagation.cpp

@@ -766,15 +766,39 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
                                entry->dst, entry->size_written))
          continue;
 
-      /* If the type sizes don't match each channel of the instruction is
-       * either extracting a portion of the constant (which could be handled
-       * with some effort but the code below doesn't) or reading multiple
-       * channels of the source at once.
+      /* If the size of the use type is larger than the size of the entry
+       * type, the entry doesn't contain all of the data that the user is
+       * trying to use.
        */
-      if (type_sz(inst->src[i].type) != type_sz(entry->dst.type))
+      if (type_sz(inst->src[i].type) > type_sz(entry->dst.type))
          continue;
 
       fs_reg val = entry->src;
+
+      /* If the size of the use type is smaller than the size of the entry,
+       * clamp the value to the range of the use type.  This enables constant
+       * copy propagation in cases like
+       *
+       *
+       *    mov(8)          g12<1>UD        0x0000000cUD
+       *    ...
+       *    mul(8)          g47<1>D         g86<8,8,1>D     g12<16,8,2>W
+       */
+      if (type_sz(inst->src[i].type) < type_sz(entry->dst.type)) {
+         if (type_sz(inst->src[i].type) != 2 || type_sz(entry->dst.type) != 4)
+            continue;
+
+         assert(inst->src[i].subnr == 0 || inst->src[i].subnr == 2);
+
+         /* When subnr is 0, we want the lower 16-bits, and when it's 2, we
+          * want the upper 16-bits. No other values of subnr are valid for a
+          * UD source.
+          */
+         const uint16_t v = inst->src[i].subnr == 2 ? val.ud >> 16 : val.ud;
+
+         val.ud = v | (uint32_t(v) << 16);
+      }
+
       val.type = inst->src[i].type;
 
       if (inst->src[i].abs) {
@@ -836,6 +860,33 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
             inst->src[i] = val;
             progress = true;
          } else if (i == 0 && inst->src[1].file != IMM) {
+            /* Don't copy propagate the constant in situations like
+             *
+             *    mov(8)          g8<1>D          0x7fffffffD
+             *    mul(8)          g16<1>D         g8<8,8,1>D      g15<16,8,2>W
+             *
+             * On platforms that only have a 32x16 multiplier, this will
+             * result in lowering the multiply to
+             *
+             *    mul(8)          g15<1>D         g14<8,8,1>D     0xffffUW
+             *    mul(8)          g16<1>D         g14<8,8,1>D     0x7fffUW
+             *    add(8)          g15.1<2>UW      g15.1<16,8,2>UW g16<16,8,2>UW
+             *
+             * On Gfx8 and Gfx9, which have the full 32x32 multiplier, it
+             * results in
+             *
+             *    mul(8)          g16<1>D         g15<16,8,2>W    0x7fffffffD
+             *
+             * Volume 2a of the Skylake PRM says:
+             *
+             *    When multiplying a DW and any lower precision integer, the
+             *    DW operand must on src0.
+             */
+            if (inst->opcode == BRW_OPCODE_MUL &&
+                type_sz(inst->src[1].type) < 4 &&
+                type_sz(val.type) == 4)
+               break;
+
             /* Fit this constant in by commuting the operands.
              * Exception: we can't do this for 32-bit integer MUL/MACH
              * because it's asymmetric.

src/intel/compiler/brw_nir.c

@@ -951,7 +951,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
    brw_nir_optimize(nir, compiler, is_scalar, true);
 
    OPT(nir_lower_doubles, softfp64, nir->options->lower_doubles_options);
-   OPT(nir_lower_int64);
+   if (OPT(nir_lower_int64)) {
+      OPT(nir_opt_algebraic);
+      OPT(nir_lower_doubles, softfp64, nir->options->lower_doubles_options);
+   }
 
    OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler);
 
@@ -1283,6 +1286,9 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
       OPT(brw_nir_opt_peephole_ffma);
    }
 
+   if (devinfo->ver >= 7 && is_scalar)
+      OPT(brw_nir_opt_peephole_imul32x16);
+
    if (OPT(nir_opt_comparison_pre)) {
       OPT(nir_copy_prop);
       OPT(nir_opt_dce);

src/intel/compiler/brw_nir.h

@@ -176,6 +176,8 @@ void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
 
 bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 
+bool brw_nir_opt_peephole_imul32x16(nir_shader *shader);
+
 void brw_nir_optimize(nir_shader *nir,
                       const struct brw_compiler *compiler,
                       bool is_scalar,

src/intel/compiler/brw_nir_opt_peephole_imul32x16.c

+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_nir.h"
+#include "compiler/nir/nir_builder.h"
+
+/**
+ * Implement a peephole pass to convert integer multiplications to imul32x16.
+ */
+
+struct pass_data {
+   struct hash_table *range_ht;
+};
+
+static void
+replace_imul_instr(nir_builder *b, nir_alu_instr *imul, unsigned small_val,
+                   nir_op new_opcode)
+{
+   assert(small_val == 0 || small_val == 1);
+
+   b->cursor = nir_before_instr(&imul->instr);
+
+   nir_alu_instr *imul_32x16 = nir_alu_instr_create(b->shader, new_opcode);
+   imul_32x16->dest.saturate = imul->dest.saturate;
+   imul_32x16->dest.write_mask = imul->dest.write_mask;
+
+   nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16);
+   nir_alu_src_copy(&imul_32x16->src[1], &imul->src[small_val], imul_32x16);
+
+   nir_ssa_dest_init(&imul_32x16->instr, &imul_32x16->dest.dest,
+                     imul->dest.dest.ssa.num_components,
+                     32, NULL);
+
+   nir_ssa_def_rewrite_uses(&imul->dest.dest.ssa,
+                            &imul_32x16->dest.dest.ssa);
+
+   nir_builder_instr_insert(b, &imul_32x16->instr);
+
+   nir_instr_remove(&imul->instr);
+   nir_instr_free(&imul->instr);
+}
+
+enum root_operation {
+   non_unary = 0,
+   integer_neg = 1 << 0,
+   integer_abs = 1 << 1,
+   integer_neg_abs = integer_neg | integer_abs,
+   invalid_root = 255
+};
+
+static enum root_operation
+signed_integer_range_analysis(nir_shader *shader, struct hash_table *range_ht,
+                              nir_ssa_scalar scalar, int *lo, int *hi)
+{
+   if (nir_ssa_scalar_is_const(scalar)) {
+      *lo = nir_ssa_scalar_as_int(scalar);
+      *hi = *lo;
+      return non_unary;
+   }
+
+   if (nir_ssa_scalar_is_alu(scalar)) {
+      switch (nir_ssa_scalar_alu_op(scalar)) {
+      case nir_op_iabs:
+         signed_integer_range_analysis(shader, range_ht,
+                                       nir_ssa_scalar_chase_alu_src(scalar, 0),
+                                       lo, hi);
+
+         if (*lo == INT32_MIN) {
+            *hi = INT32_MAX;
+         } else {
+            const int32_t a = abs(*lo);
+            const int32_t b = abs(*hi);
+
+            *lo = MIN2(a, b);
+            *hi = MAX2(a, b);
+         }
+
+         /* Absolute value wipes out any inner negations, and it is redundant
+          * with any inner absolute values.
+          */
+         return integer_abs;
+
+      case nir_op_ineg: {
+         const enum root_operation root =
+            signed_integer_range_analysis(shader, range_ht,
+                                          nir_ssa_scalar_chase_alu_src(scalar, 0),
+                                          lo, hi);
+
+         if (*lo == INT32_MIN) {
+            *hi = INT32_MAX;
+         } else {
+            const int32_t a = -(*lo);
+            const int32_t b = -(*hi);
+
+            *lo = MIN2(a, b);
+            *hi = MAX2(a, b);
+         }
+
+         /* Negation of a negation cancels out, but negation of absolute value
+          * must preserve the integer_abs bit.
+          */
+         return root ^ integer_neg;
+      }
+
+      case nir_op_imax: {
+         int src0_lo, src0_hi;
+         int src1_lo, src1_hi;
+
+         signed_integer_range_analysis(shader, range_ht,
+                                       nir_ssa_scalar_chase_alu_src(scalar, 0),
+                                       &src0_lo, &src0_hi);
+         signed_integer_range_analysis(shader, range_ht,
+                                       nir_ssa_scalar_chase_alu_src(scalar, 1),
+                                       &src1_lo, &src1_hi);
+
+         *lo = MAX2(src0_lo, src1_lo);
+         *hi = MAX2(src0_hi, src1_hi);
+         break;
+      }
+
+      case nir_op_imin: {
+         int src0_lo, src0_hi;
+         int src1_lo, src1_hi;
+
+         signed_integer_range_analysis(shader, range_ht,
+                                       nir_ssa_scalar_chase_alu_src(scalar, 0),
+                                       &src0_lo, &src0_hi);
+         signed_integer_range_analysis(shader, range_ht,
+                                       nir_ssa_scalar_chase_alu_src(scalar, 1),
+                                       &src1_lo, &src1_hi);
+
+         *lo = MIN2(src0_lo, src1_lo);
+         *hi = MIN2(src0_hi, src1_hi);
+         break;
+      }
+
+      default:
+         break;
+      }
+   }
+
+   /* Any value with the sign-bit set is problematic. Consider the case when
+    * bound is 0x80000000. As an unsigned value, this means the value must be
+    * in the range [0, 0x80000000]. As a signed value, it means the value must
+    * be in the range [0, INT_MAX] or it must be INT_MIN.
+    *
+    * If bound is -2, it means the value is either in the range [INT_MIN, -2]
+    * or it is in the range [0, INT_MAX].
+    *
+    * This function only returns a single, contiguous range. The union of the
+    * two ranges for any value of bound with the sign-bit set is [INT_MIN,
+    * INT_MAX].
+    */
+   const int32_t bound = nir_unsigned_upper_bound(shader, range_ht,
+                                                     scalar, NULL);
+   if (bound < 0) {
+      *lo = INT32_MIN;
+      *hi = INT32_MAX;
+   } else {
+      *lo = 0;
+      *hi = bound;
+   }
+
+   return non_unary;
+}
+
+static bool
+brw_nir_opt_peephole_imul32x16_instr(nir_builder *b,
+                                     nir_instr *instr,
+                                     void *cb_data)
+{
+   struct pass_data *d = (struct pass_data *) cb_data;
+   struct hash_table *range_ht = d->range_ht;
+
+   if (instr->type != nir_instr_type_alu)
+      return false;
+
+   nir_alu_instr *imul = nir_instr_as_alu(instr);
+   if (imul->op != nir_op_imul)
+      return false;
+
+   if (imul->dest.dest.ssa.bit_size != 32)
+      return false;
+
+   nir_op new_opcode = nir_num_opcodes;
+
+   unsigned i;
+   for (i = 0; i < 2; i++) {
+      if (!nir_src_is_const(imul->src[i].src))
+         continue;
+
+      int64_t lo = INT64_MAX;
+      int64_t hi = INT64_MIN;
+
+      for (unsigned comp = 0; comp < imul->dest.dest.ssa.num_components; comp++) {
+         int64_t v = nir_src_comp_as_int(imul->src[i].src, comp);
+
+         if (v < lo)
+            lo = v;
+
+         if (v > hi)
+            hi = v;
+      }
+
+      if (lo >= INT16_MIN && hi <= INT16_MAX) {
+         new_opcode = nir_op_imul_32x16;
+         break;
+      } else if (lo >= 0 && hi <= UINT16_MAX) {
+         new_opcode = nir_op_umul_32x16;
+         break;
+      }
+   }
+
+   if (new_opcode != nir_num_opcodes) {
+      replace_imul_instr(b, imul, i, new_opcode);
+      return true;
+   }
+
+   if (imul->dest.dest.ssa.num_components > 1)
+      return false;
+
+   const nir_ssa_scalar imul_scalar = { &imul->dest.dest.ssa, 0 };
+   int idx = -1;
+   enum root_operation prev_root = invalid_root;
+
+   for (i = 0; i < 2; i++) {
+      /* All constants were previously processed.  There is nothing more to
+       * learn from a constant here.
+       */
+      if (imul->src[i].src.ssa->parent_instr->type == nir_instr_type_load_const)
+         continue;
+
+      nir_ssa_scalar scalar = nir_ssa_scalar_chase_alu_src(imul_scalar, i);
+      int lo = INT32_MIN;
+      int hi = INT32_MAX;
+
+      const enum root_operation root =
+         signed_integer_range_analysis(b->shader, range_ht, scalar, &lo, &hi);
+
+      /* Copy propagation (in the backend) has trouble handling cases like
+       *
+       *    mov(8)          g60<1>D         -g59<8,8,1>D
+       *    mul(8)          g61<1>D         g63<8,8,1>D     g60<16,8,2>W
+       *
+       * If g59 had absolute value instead of negation, even improved copy
+       * propagation would not be able to make progress.
+       *
+       * In cases where both sources to the integer multiplication can fit in
+       * 16-bits, choose the source that does not have a source modifier.
+       */
+      if (root < prev_root) {
+         if (lo >= INT16_MIN && hi <= INT16_MAX) {
+            new_opcode = nir_op_imul_32x16;
+            idx = i;
+            prev_root = root;
+
+            if (root == non_unary)
+               break;
+         } else if (lo >= 0 && hi <= UINT16_MAX) {
+            new_opcode = nir_op_umul_32x16;
+            idx = i;
+            prev_root = root;
+
+            if (root == non_unary)
+               break;
+         }
+      }
+   }
+
+   if (new_opcode == nir_num_opcodes) {
+      assert(idx == -1);
+      assert(prev_root == invalid_root);
+      return false;
+   }
+
+   assert(idx != -1);
+   assert(prev_root != invalid_root);
+
+   replace_imul_instr(b, imul, idx, new_opcode);
+   return true;
+}
+
+bool
+brw_nir_opt_peephole_imul32x16(nir_shader *shader)
+{
+   struct pass_data cb_data;
+
+   cb_data.range_ht = _mesa_pointer_hash_table_create(NULL);
+
+   bool progress = nir_shader_instructions_pass(shader,
+                                                brw_nir_opt_peephole_imul32x16_instr,
+                                                nir_metadata_block_index |
+                                                nir_metadata_dominance,
+                                                &cb_data);
+
+   _mesa_hash_table_destroy(cb_data.range_ht, NULL);
+
+   return progress;
+}
+

src/intel/compiler/meson.build

@@ -98,6 +98,7 @@ libintel_compiler_files = files(
   'brw_nir_lower_shading_rate_output.c',
   'brw_nir_lower_storage_image.c',
   'brw_nir_opt_peephole_ffma.c',
+  'brw_nir_opt_peephole_imul32x16.c',
   'brw_nir_rt.h',
   'brw_nir_rt.c',
   'brw_nir_rt_builder.h',

src/intel/dev/intel_device_info.c

@@ -1955,10 +1955,9 @@ intel_i915_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
       update_cs_workgroup_threads(devinfo);
    }
 
-   int timestamp_frequency;
-   if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
-                &timestamp_frequency))
-      devinfo->timestamp_frequency = timestamp_frequency;
+   int val;
+   if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY, &val))
+      devinfo->timestamp_frequency = val;
    else if (devinfo->ver >= 10) {
       mesa_loge("Kernel 4.15 required to read the CS timestamp frequency.");
       return false;
@@ -2005,6 +2004,13 @@ intel_i915_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
    get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE, &devinfo->gtt_size);
    devinfo->has_tiling_uapi = has_get_tiling(fd);
 
+   if (getparam(fd, I915_PARAM_MMAP_GTT_VERSION, &val))
+      devinfo->has_mmap_offset = val >= 4;
+   if (getparam(fd, I915_PARAM_HAS_USERPTR_PROBE, &val))
+      devinfo->has_userptr_probe = val;
+   if (getparam(fd, I915_PARAM_HAS_CONTEXT_ISOLATION, &val))
+      devinfo->has_context_isolation = val;
+
    return true;
 }
 

src/intel/dev/intel_device_info.h

@@ -146,6 +146,9 @@ struct intel_device_info
    bool has_local_mem;
    bool has_lsc;
    bool has_mesh_shading;
+   bool has_mmap_offset;
+   bool has_userptr_probe;
+   bool has_context_isolation;
 
    /**
     * \name Intel hardware quirks

src/intel/perf/intel_perf.c

@@ -580,18 +580,9 @@ load_pipeline_statistic_metrics(struct intel_perf_config *perf_cfg,
 static int
 i915_perf_version(int drm_fd)
 {
-   int tmp;
-   drm_i915_getparam_t gp = {
-      .param = I915_PARAM_PERF_REVISION,
-      .value = &tmp,
-   };
-
-   int ret = intel_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-   /* Return 0 if this getparam is not supported, the first version supported
-    * is 1.
-    */
-   return ret < 0 ? 0 : tmp;
+   int tmp = 0;
+   intel_gem_get_param(drm_fd, I915_PARAM_PERF_REVISION, &tmp);
+   return tmp;
 }
 
 static void

src/intel/tools/intel_dump_gpu.c

@@ -45,6 +45,7 @@
 
 #include "dev/intel_debug.h"
 #include "dev/intel_device_info.h"
+#include "common/intel_gem.h"
 #include "util/macros.h"
 
 static int close_init_helper(int fd);
@@ -410,16 +411,12 @@ close(int fd)
 static int
 get_pci_id(int fd, int *pci_id)
 {
-   struct drm_i915_getparam gparam;
-
    if (device_override) {
       *pci_id = device;
       return 0;
    }
 
-   gparam.param = I915_PARAM_CHIPSET_ID;
-   gparam.value = pci_id;
-   return libc_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gparam);
+   return intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, pci_id) ? 0 : -1;
 }
 
 static void

src/intel/tools/meson.build

@@ -118,7 +118,7 @@ libintel_dump_gpu = shared_library(
   ),
   dependencies : [dep_dl, idep_mesautil],
   include_directories : [inc_include, inc_src, inc_intel],
-  link_with : libintel_dev,
+  link_with : [libintel_dev, libintel_common],
   c_args : [no_override_init_args],
   gnu_symbol_visibility : 'hidden',
   install_dir : get_option('libexecdir'),

src/intel/vulkan/anv_blorp.c

@@ -263,33 +263,6 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
    }
 }
 
-static bool
-get_blorp_surf_for_anv_shadow_image(const struct anv_device *device,
-                                    const struct anv_image *image,
-                                    VkImageAspectFlags aspect,
-                                    struct blorp_surf *blorp_surf)
-{
-
-   const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
-   if (!anv_surface_is_valid(&image->planes[plane].shadow_surface))
-      return false;
-
-   const struct anv_surface *surface = &image->planes[plane].shadow_surface;
-   const struct anv_address address =
-      anv_image_address(image, &surface->memory_range);
-
-   *blorp_surf = (struct blorp_surf) {
-      .surf = &surface->isl,
-      .addr = {
-         .buffer = address.bo,
-         .offset = address.offset,
-         .mocs = anv_mocs(device, address.bo, ISL_SURF_USAGE_RENDER_TARGET_BIT),
-      },
-   };
-
-   return true;
-}
-
 static void
 copy_image(struct anv_cmd_buffer *cmd_buffer,
            struct blorp_batch *batch,
@@ -358,20 +331,6 @@ copy_image(struct anv_cmd_buffer *cmd_buffer,
                        dstOffset.x, dstOffset.y,
                        extent.width, extent.height);
          }
-
-         struct blorp_surf dst_shadow_surf;
-         if (get_blorp_surf_for_anv_shadow_image(cmd_buffer->device,
-                                                 dst_image,
-                                                 1UL << aspect_bit,
-                                                 &dst_shadow_surf)) {
-            for (unsigned i = 0; i < layer_count; i++) {
-               blorp_copy(batch, &src_surf, src_level, src_base_layer + i,
-                          &dst_shadow_surf, dst_level, dst_base_layer + i,
-                          srcOffset.x, srcOffset.y,
-                          dstOffset.x, dstOffset.y,
-                          extent.width, extent.height);
-            }
-         }
       }
    } else {
       struct blorp_surf src_surf, dst_surf;
@@ -394,19 +353,6 @@ copy_image(struct anv_cmd_buffer *cmd_buffer,
                     dstOffset.x, dstOffset.y,
                     extent.width, extent.height);
       }
-
-      struct blorp_surf dst_shadow_surf;
-      if (get_blorp_surf_for_anv_shadow_image(cmd_buffer->device,
-                                              dst_image, dst_mask,
-                                              &dst_shadow_surf)) {
-         for (unsigned i = 0; i < layer_count; i++) {
-            blorp_copy(batch, &src_surf, src_level, src_base_layer + i,
-                       &dst_shadow_surf, dst_level, dst_base_layer + i,
-                       srcOffset.x, srcOffset.y,
-                       dstOffset.x, dstOffset.y,
-                       extent.width, extent.height);
-         }
-      }
    }
 }
 
@@ -527,8 +473,6 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
                                  buffer_layout.row_stride_B, buffer_format,
                                  false, &buffer.surf, &buffer_isl_surf);
 
-   bool dst_has_shadow = false;
-   struct blorp_surf dst_shadow_surf;
    if (&image == dst) {
       /* In this case, the source is the buffer and, since blorp takes its
        * copy dimensions in terms of the source format, we have to use the
@@ -542,11 +486,6 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
                                         aspect, dst->surf.aux_usage,
                                         dst->level,
                                         dst->offset.z, extent.depth);
-
-      dst_has_shadow =
-         get_blorp_surf_for_anv_shadow_image(cmd_buffer->device,
-                                             anv_image, aspect,
-                                             &dst_shadow_surf);
    }
 
    for (unsigned z = 0; z < extent.depth; z++) {
@@ -555,14 +494,6 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
                  src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
                  extent.width, extent.height);
 
-      if (dst_has_shadow) {
-         blorp_copy(batch, &src->surf, src->level, src->offset.z,
-                    &dst_shadow_surf, dst->level, dst->offset.z,
-                    src->offset.x, src->offset.y,
-                    dst->offset.x, dst->offset.y,
-                    extent.width, extent.height);
-      }
-
       image.offset.z++;
       buffer.surf.addr.offset += buffer_layout.image_stride_B;
    }
@@ -1063,7 +994,7 @@ void anv_CmdClearDepthStencilImage(
    anv_blorp_batch_init(cmd_buffer, &batch, 0);
    assert((batch.flags & BLORP_BATCH_USE_COMPUTE) == 0);
 
-   struct blorp_surf depth, stencil, stencil_shadow;
+   struct blorp_surf depth, stencil;
    if (image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
       get_blorp_surf_for_anv_image(cmd_buffer->device,
                                    image, VK_IMAGE_ASPECT_DEPTH_BIT,
@@ -1073,17 +1004,11 @@ void anv_CmdClearDepthStencilImage(
       memset(&depth, 0, sizeof(depth));
    }
 
-   bool has_stencil_shadow = false;
    if (image->vk.aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
       get_blorp_surf_for_anv_image(cmd_buffer->device,
                                    image, VK_IMAGE_ASPECT_STENCIL_BIT,
                                    VK_IMAGE_USAGE_TRANSFER_DST_BIT,
                                    imageLayout, ISL_AUX_USAGE_NONE, &stencil);
-
-      has_stencil_shadow =
-         get_blorp_surf_for_anv_shadow_image(cmd_buffer->device, image,
-                                             VK_IMAGE_ASPECT_STENCIL_BIT,
-                                             &stencil_shadow);
    } else {
       memset(&stencil, 0, sizeof(stencil));
    }
@@ -1115,17 +1040,6 @@ void anv_CmdClearDepthStencilImage(
                                    clear_depth, pDepthStencil->depth,
                                    clear_stencil ? 0xff : 0,
                                    pDepthStencil->stencil);
-
-         if (clear_stencil && has_stencil_shadow) {
-            union isl_color_value stencil_color = {
-               .u32 = { pDepthStencil->stencil, },
-            };
-            blorp_clear(&batch, &stencil_shadow,
-                        ISL_FORMAT_R8_UINT, ISL_SWIZZLE_IDENTITY,
-                        level, base_layer, layer_count,
-                        0, 0, level_width, level_height,
-                        stencil_color, 0 /* color_write_disable */);
-         }
       }
    }
 
@@ -1484,63 +1398,6 @@ void anv_CmdResolveImage2(
    }
 }
 
-void
-anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
-                         const struct anv_image *image,
-                         VkImageAspectFlagBits aspect,
-                         uint32_t base_level, uint32_t level_count,
-                         uint32_t base_layer, uint32_t layer_count)
-{
-   struct blorp_batch batch;
-   anv_blorp_batch_init(cmd_buffer, &batch, 0);
-
-   /* We don't know who touched the main surface last so flush a bunch of
-    * caches to ensure we get good data.
-    */
-   anv_add_pending_pipe_bits(cmd_buffer,
-                             ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
-                             ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
-                             ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
-                             ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT,
-                             "before copy_to_shadow");
-
-   struct blorp_surf surf;
-   get_blorp_surf_for_anv_image(cmd_buffer->device,
-                                image, aspect,
-                                VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
-                                VK_IMAGE_LAYOUT_GENERAL,
-                                ISL_AUX_USAGE_NONE, &surf);
-   assert(surf.aux_usage == ISL_AUX_USAGE_NONE);
-
-   struct blorp_surf shadow_surf;
-   get_blorp_surf_for_anv_shadow_image(cmd_buffer->device,
-                                       image, aspect, &shadow_surf);
-
-   for (uint32_t l = 0; l < level_count; l++) {
-      const uint32_t level = base_level + l;
-
-      const VkExtent3D extent = vk_image_mip_level_extent(&image->vk, level);
-
-      if (image->vk.image_type == VK_IMAGE_TYPE_3D)
-         layer_count = extent.depth;
-
-      for (uint32_t a = 0; a < layer_count; a++) {
-         const uint32_t layer = base_layer + a;
-
-         blorp_copy(&batch, &surf, level, layer,
-                    &shadow_surf, level, layer,
-                    0, 0, 0, 0, extent.width, extent.height);
-      }
-   }
-
-   /* We just wrote to the buffer with the render cache.  Flush it. */
-   anv_add_pending_pipe_bits(cmd_buffer,
-                             ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT,
-                             "after copy_to_shadow");
-
-   anv_blorp_batch_finish(&batch);
-}
-
 void
 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
                       const struct anv_image *image,
@@ -1639,23 +1496,6 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
                              ANV_PIPE_END_OF_PIPE_SYNC_BIT,
                              "after clear DS");
 
-   struct blorp_surf stencil_shadow;
-   if ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
-       get_blorp_surf_for_anv_shadow_image(cmd_buffer->device, image,
-                                           VK_IMAGE_ASPECT_STENCIL_BIT,
-                                           &stencil_shadow)) {
-      union isl_color_value stencil_color = {
-         .u32 = { stencil_value },
-      };
-      blorp_clear(&batch, &stencil_shadow,
-                  ISL_FORMAT_R8_UINT, ISL_SWIZZLE_IDENTITY,
-                  level, base_layer, layer_count,
-                  area.offset.x, area.offset.y,
-                  area.offset.x + area.extent.width,
-                  area.offset.y + area.extent.height,
-                  stencil_color, 0 /* color_write_disable */);
-   }
-
    anv_blorp_batch_finish(&batch);
 }
 

src/intel/vulkan/anv_device.c

@@ -741,41 +741,43 @@ static VkResult
 anv_i915_physical_device_get_parameters(struct anv_physical_device *device)
 {
    VkResult result = VK_SUCCESS;
-   int fd = device->local_fd;
+   int val, fd = device->local_fd;
 
-   if (!anv_gem_get_param(fd, I915_PARAM_HAS_WAIT_TIMEOUT)) {
+   if (!intel_gem_get_param(fd, I915_PARAM_HAS_WAIT_TIMEOUT, &val) || !val) {
        result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
                           "kernel missing gem wait");
        return result;
    }
 
-   if (!anv_gem_get_param(fd, I915_PARAM_HAS_EXECBUF2)) {
+   if (!intel_gem_get_param(fd, I915_PARAM_HAS_EXECBUF2, &val) || !val) {
       result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
                          "kernel missing execbuf2");
       return result;
    }
 
    if (!device->info.has_llc &&
-       anv_gem_get_param(fd, I915_PARAM_MMAP_VERSION) < 1) {
+       (!intel_gem_get_param(fd, I915_PARAM_MMAP_VERSION, &val) || val < 1)) {
        result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
                           "kernel missing wc mmap");
        return result;
    }
 
-   if (!anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN)) {
+   if (!intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN, &val) || !val) {
       result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
                          "kernel missing softpin");
       return result;
    }
 
-   if (!anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_FENCE_ARRAY)) {
+   if (!intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_FENCE_ARRAY, &val) || !val) {
       result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
                          "kernel missing syncobj support");
       return result;
    }
 
-   device->has_exec_async = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_ASYNC);
-   device->has_exec_capture = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_CAPTURE);
+   if (intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_ASYNC, &val))
+      device->has_exec_async = val;
+   if (intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_CAPTURE, &val))
+      device->has_exec_capture = val;
 
    /* Start with medium; sorted low to high */
    const VkQueueGlobalPriorityKHR priorities[] = {
@@ -791,17 +793,8 @@ anv_i915_physical_device_get_parameters(struct anv_physical_device *device)
       device->max_context_priority = priorities[i];
    }
 
-   device->has_context_isolation =
-      anv_gem_get_param(fd, I915_PARAM_HAS_CONTEXT_ISOLATION);
-
-   device->has_exec_timeline =
-      anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_TIMELINE_FENCES);
-
-   device->has_mmap_offset =
-      anv_gem_get_param(fd, I915_PARAM_MMAP_GTT_VERSION) >= 4;
-
-   device->has_userptr_probe =
-      anv_gem_get_param(fd, I915_PARAM_HAS_USERPTR_PROBE);
+   if (intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_TIMELINE_FENCES, &val))
+      device->has_exec_timeline = val;
 
    return result;
 }
@@ -960,7 +953,7 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
    device->compiler->shader_debug_log = compiler_debug_log;
    device->compiler->shader_perf_log = compiler_perf_log;
    device->compiler->constant_buffer_0_is_relative =
-      !device->has_context_isolation;
+      !device->info.has_context_isolation;
    device->compiler->supports_shader_constants = true;
    device->compiler->indirect_ubos_use_sampler = device->info.ver < 12;
 
@@ -975,10 +968,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
    if (instance->vk.enabled_extensions.KHR_display) {
       master_fd = open(primary_path, O_RDWR | O_CLOEXEC);
       if (master_fd >= 0) {
-         /* prod the device with a GETPARAM call which will fail if
-          * we don't have permission to even render on this device
-          */
-         if (anv_gem_get_param(master_fd, I915_PARAM_CHIPSET_ID) == 0) {
+         /* fail if we don't have permission to even render on this device */
+         if (!intel_gem_can_render_on_fd(master_fd)) {
             close(master_fd);
             master_fd = -1;
          }
@@ -4308,7 +4299,7 @@ VkResult anv_MapMemory(
 
    /* GEM will fail to map if the offset isn't 4k-aligned.  Round down. */
    uint64_t map_offset;
-   if (!device->physical->has_mmap_offset)
+   if (!device->physical->info.has_mmap_offset)
       map_offset = offset & ~4095ull;
    else
       map_offset = 0;

src/intel/vulkan/anv_gem.c

@@ -146,7 +146,7 @@ anv_gem_mmap(struct anv_device *device, uint32_t gem_handle,
              uint64_t offset, uint64_t size, uint32_t flags)
 {
    void *map;
-   if (device->physical->has_mmap_offset)
+   if (device->physical->info.has_mmap_offset)
       map = anv_gem_mmap_offset(device, gem_handle, offset, size, flags);
    else
       map = anv_gem_mmap_legacy(device, gem_handle, offset, size, flags);
@@ -176,7 +176,7 @@ anv_gem_userptr(struct anv_device *device, void *mem, size_t size)
       .flags = 0,
    };
 
-   if (device->physical->has_userptr_probe)
+   if (device->physical->info.has_userptr_probe)
       userptr.flags |= I915_USERPTR_PROBE;
 
    int ret = intel_ioctl(device->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
@@ -278,23 +278,6 @@ anv_gem_set_tiling(struct anv_device *device,
    return ret;
 }
 
-int
-anv_gem_get_param(int fd, uint32_t param)
-{
-   int tmp;
-
-   drm_i915_getparam_t gp = {
-      .param = param,
-      .value = &tmp,
-   };
-
-   int ret = intel_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-   if (ret == 0)
-      return tmp;
-
-   return 0;
-}
-
 bool
 anv_gem_has_context_priority(int fd, VkQueueGlobalPriorityKHR priority)
 {

src/intel/vulkan/anv_gem_stubs.c

@@ -118,12 +118,6 @@ anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle,
    return 0;
 }
 
-int
-anv_gem_get_param(int fd, uint32_t param)
-{
-   unreachable("Unused");
-}
-
 int
 anv_gem_set_context_param(int fd, uint32_t context, uint32_t param, uint64_t value)
 {

src/intel/vulkan/anv_image.c

@@ -321,46 +321,6 @@ add_surface(struct anv_device *device,
                              &surf->memory_range);
 }
 
-/**
- * Do hardware limitations require the image plane to use a shadow surface?
- *
- * If hardware limitations force us to use a shadow surface, then the same
- * limitations may also constrain the tiling of the primary surface; therefore
- * parameter @a inout_primary_tiling_flags.
- *
- * If the image plane is a separate stencil plane and if the user provided
- * VkImageStencilUsageCreateInfo, then @a usage must be stencilUsage.
- *
- * @see anv_image::planes[]::shadow_surface
- */
-static bool
-anv_image_plane_needs_shadow_surface(const struct intel_device_info *devinfo,
-                                     struct anv_format_plane plane_format,
-                                     VkImageTiling vk_tiling,
-                                     VkImageUsageFlags vk_plane_usage,
-                                     VkImageCreateFlags vk_create_flags,
-                                     isl_tiling_flags_t *inout_primary_tiling_flags)
-{
-   if (devinfo->ver <= 8 &&
-       (vk_create_flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
-       vk_tiling == VK_IMAGE_TILING_OPTIMAL) {
-      /* We must fallback to a linear surface because we may not be able to
-       * correctly handle the offsets if tiled. (On gfx9,
-       * RENDER_SURFACE_STATE::X/Y Offset are sufficient). To prevent garbage
-       * performance while texturing, we maintain a tiled shadow surface.
-       */
-      assert(isl_format_is_compressed(plane_format.isl_format));
-
-      if (inout_primary_tiling_flags) {
-         *inout_primary_tiling_flags = ISL_TILING_LINEAR_BIT;
-      }
-
-      return true;
-   }
-
-   return false;
-}
-
 static bool
 can_fast_clear_with_non_zero_color(const struct intel_device_info *devinfo,
                                    const struct anv_image *image,
@@ -868,42 +828,6 @@ add_aux_surface_if_supported(struct anv_device *device,
    return VK_SUCCESS;
 }
 
-static VkResult
-add_shadow_surface(struct anv_device *device,
-                   struct anv_image *image,
-                   uint32_t plane,
-                   struct anv_format_plane plane_format,
-                   uint32_t stride,
-                   VkImageUsageFlags vk_plane_usage)
-{
-   ASSERTED bool ok;
-
-   ok = isl_surf_init(&device->isl_dev,
-                      &image->planes[plane].shadow_surface.isl,
-                     .dim = vk_to_isl_surf_dim[image->vk.image_type],
-                     .format = plane_format.isl_format,
-                     .width = image->vk.extent.width,
-                     .height = image->vk.extent.height,
-                     .depth = image->vk.extent.depth,
-                     .levels = image->vk.mip_levels,
-                     .array_len = image->vk.array_layers,
-                     .samples = image->vk.samples,
-                     .min_alignment_B = 0,
-                     .row_pitch_B = stride,
-                     .usage = ISL_SURF_USAGE_TEXTURE_BIT |
-                              (vk_plane_usage & ISL_SURF_USAGE_CUBE_BIT),
-                     .tiling_flags = ISL_TILING_ANY_MASK);
-
-   /* isl_surf_init() will fail only if provided invalid input. Invalid input
-    * here is illegal in Vulkan.
-    */
-   assert(ok);
-
-   return add_surface(device, image, &image->planes[plane].shadow_surface,
-                      ANV_IMAGE_MEMORY_BINDING_PLANE_0 + plane,
-                      ANV_OFFSET_IMPLICIT);
-}
-
 /**
  * Initialize the anv_image::*_surface selected by \a aspect. Then update the
  * image's memory requirements (that is, the image's size and alignment).
@@ -1045,13 +969,6 @@ check_memory_bindings(const struct anv_device *device,
                          .test_surface = &plane->primary_surface,
                          .expect_binding = primary_binding);
 
-      /* Check shadow surface */
-      if (anv_surface_is_valid(&plane->shadow_surface)) {
-         check_memory_range(accum_ranges,
-                            .test_surface = &plane->shadow_surface,
-                            .expect_binding = primary_binding);
-      }
-
       /* Check aux_surface */
       if (anv_surface_is_valid(&plane->aux_surface)) {
          enum anv_image_memory_binding binding = primary_binding;
@@ -1159,7 +1076,6 @@ check_drm_format_mod(const struct anv_device *device,
       assert(isl_layout->txc == ISL_TXC_NONE);
       assert(isl_layout->colorspace == ISL_COLORSPACE_LINEAR ||
              isl_layout->colorspace == ISL_COLORSPACE_SRGB);
-      assert(!anv_surface_is_valid(&plane->shadow_surface));
 
       if (isl_mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
          /* Reject DISJOINT for consistency with the GL driver. */
@@ -1207,28 +1123,12 @@ add_all_surfaces_implicit_layout(
          choose_isl_surf_usage(image->vk.create_flags, vk_usage,
                                isl_extra_usage_flags, aspect);
 
-      /* Must call this before adding any surfaces because it may modify
-       * isl_tiling_flags.
-       */
-      bool needs_shadow =
-         anv_image_plane_needs_shadow_surface(devinfo, plane_format,
-                                              image->vk.tiling, vk_usage,
-                                              image->vk.create_flags,
-                                              &isl_tiling_flags);
-
       result = add_primary_surface(device, image, plane, plane_format,
                                    ANV_OFFSET_IMPLICIT, stride,
                                    isl_tiling_flags, isl_usage);
       if (result != VK_SUCCESS)
          return result;
 
-      if (needs_shadow) {
-         result = add_shadow_surface(device, image, plane, plane_format,
-                                     stride, vk_usage);
-         if (result != VK_SUCCESS)
-            return result;
-      }
-
       /* Disable aux if image supports export without modifiers. */
       if (image->vk.external_handle_types != 0 &&
           image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
@@ -2474,20 +2374,6 @@ anv_image_fill_surface_state(struct anv_device *device,
    struct isl_view view = *view_in;
    view.usage |= view_usage;
 
-   /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
-    * compressed surface with a shadow surface, we use the shadow instead of
-    * the primary surface.  The shadow surface will be tiled, unlike the main
-    * surface, so it should get significantly better performance.
-    */
-   if (anv_surface_is_valid(&image->planes[plane].shadow_surface) &&
-       isl_format_is_compressed(view.format) &&
-       (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
-      assert(isl_format_is_compressed(surface->isl.format));
-      assert(surface->isl.tiling == ISL_TILING_LINEAR);
-      assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
-      surface = &image->planes[plane].shadow_surface;
-   }
-
    if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
       view.swizzle = anv_swizzle_for_render(view.swizzle);
 

src/intel/vulkan/anv_private.h

@@ -963,9 +963,6 @@ struct anv_physical_device {
     bool                                        has_exec_async;
     bool                                        has_exec_capture;
     VkQueueGlobalPriorityKHR                    max_context_priority;
-    bool                                        has_context_isolation;
-    bool                                        has_mmap_offset;
-    bool                                        has_userptr_probe;
     uint64_t                                    gtt_size;
 
     bool                                        always_use_bindless;
@@ -1349,7 +1346,6 @@ int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
 bool anv_gem_has_context_priority(int fd, VkQueueGlobalPriorityKHR priority);
 int anv_gem_set_context_param(int fd, uint32_t context, uint32_t param,
                               uint64_t value);
-int anv_gem_get_param(int fd, uint32_t param);
 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
 int anv_gem_context_get_reset_stats(int fd, int context,
                                     uint32_t *active, uint32_t *pending);
@@ -3441,13 +3437,6 @@ struct anv_image {
    struct anv_image_plane {
       struct anv_surface primary_surface;
 
-      /**
-       * A surface which shadows the main surface and may have different
-       * tiling. This is used for sampling using a tiling that isn't supported
-       * for other operations.
-       */
-      struct anv_surface shadow_surface;
-
       /**
        * The base aux usage for this image.  For color images, this can be
        * either CCS_E or CCS_D depending on whether or not we can reliably
@@ -3757,13 +3746,6 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
                  enum isl_aux_op ccs_op, union isl_color_value *clear_value,
                  bool predicate);
 
-void
-anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
-                         const struct anv_image *image,
-                         VkImageAspectFlagBits aspect,
-                         uint32_t base_level, uint32_t level_count,
-                         uint32_t base_layer, uint32_t layer_count);
-
 enum isl_aux_state ATTRIBUTE_PURE
 anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
                         const struct anv_image *image,