.gitlab-ci/test-source-dep.yml

@@ -443,6 +443,7 @@
       when: on_success
     - changes: &radeonsi_file_list
       - src/gallium/drivers/radeonsi/**/*
+      - src/gallium/include/winsys/**/*
       - src/gallium/winsys/amdgpu/**/*
       - src/amd/*
       - src/amd/addrlib/**/*
@@ -469,7 +470,6 @@
       when: on_success
     - changes: &radeon_vcn_file_list
       - src/gallium/frontends/va/**/*
-      - src/gallium/drivers/radeon/**/*
       when: on_success
     - when: never
 

docs/drivers/zink.rst

@@ -37,6 +37,9 @@ Here's a list of those requirements:
 * Device extensions:
 
   * `VK_KHR_maintenance1`_
+  * ``VK_KHR_create_renderpass2``
+  * ``VK_KHR_imageless_framebuffer``
+  * ``VK_KHR_timeline_semaphore``
   * `VK_EXT_custom_border_color`_
   * `VK_EXT_provoking_vertex`_
   * `VK_EXT_line_rasterization`_, with the following ``VkPhysicalDeviceLineRasterizationFeaturesEXT``:

docs/gallium/screen.rst

@@ -699,7 +699,7 @@ DCL CONST[3][0]          # declare first vector of constbuf 3
 MOV OUT[0], CONST[0][3]  # copy vector 3 of constbuf 0
 
 * ``PIPE_SHADER_CAP_MAX_TEMPS``: The maximum number of temporary registers.
-* ``PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED``: Whether the continue opcode is supported.
+* ``PIPE_SHADER_CAP_CONT_SUPPORTED``: Whether continue is supported.
 * ``PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR``: Whether indirect addressing
   of the input file is supported.
 * ``PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR``: Whether indirect addressing
@@ -732,11 +732,11 @@ MOV OUT[0], CONST[0][3]  # copy vector 3 of constbuf 0
   program.  It should be one of the ``pipe_shader_ir`` enum values.
 * ``PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS``: The maximum number of texture
   sampler views. Must not be lower than PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS.
-* ``PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED``: Whether double precision rounding
+* ``PIPE_SHADER_CAP_DROUND_SUPPORTED``: Whether double precision rounding
   is supported. If it is, DTRUNC/DCEIL/DFLR/DROUND opcodes may be used.
-* ``PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED``: Whether DFRACEXP and
+* ``PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED``: Whether DFRACEXP and
   DLDEXP are supported.
-* ``PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED``: Whether LDEXP is supported.
+* ``PIPE_SHADER_CAP_LDEXP_SUPPORTED``: Whether LDEXP is supported.
 * ``PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED``: Whether FMA and DFMA (doubles only)
   are supported.
 * ``PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE``: Whether the driver doesn't

meson_options.txt

@@ -357,7 +357,7 @@ option(
 option(
   'draw-use-llvm',
   type : 'boolean',
-  value : 'true',
+  value : true,
   description : 'Whether to use LLVM for the Gallium draw module, if LLVM is included.'
 )
 option(

src/amd/compiler/aco_opcodes.py

@@ -385,8 +385,8 @@ for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass
 SOPK = {
   # GFX6, GFX7, GFX8, GFX9, GFX10, name
    (0x00, 0x00, 0x00, 0x00, 0x00, "s_movk_i32"),
-   (  -1,   -1,   -1,   -1, 0x01, "s_version"), # GFX10+
-   (0x02, 0x02, 0x01, 0x01, 0x02, "s_cmovk_i32"), # GFX8_GFX9
+   (  -1,   -1,   -1,   -1, 0x01, "s_version"),
+   (0x02, 0x02, 0x01, 0x01, 0x02, "s_cmovk_i32"),
    (0x03, 0x03, 0x02, 0x02, 0x03, "s_cmpk_eq_i32"),
    (0x04, 0x04, 0x03, 0x03, 0x04, "s_cmpk_lg_i32"),
    (0x05, 0x05, 0x04, 0x04, 0x05, "s_cmpk_gt_i32"),

src/amd/drm-shim/meson.build

@@ -20,7 +20,7 @@
 # IN THE SOFTWARE.
 
 libradeon_noop_drm_shim = shared_library(
-  ['radeon_noop_drm_shim'],
+  'radeon_noop_drm_shim',
   'radeon_noop_drm_shim.c',
   include_directories: [inc_include, inc_src, inc_amd],
   dependencies: dep_drm_shim,

src/amd/vulkan/radv_nir_lower_ray_queries.c

@@ -691,7 +691,7 @@ lower_rq_proceed(nir_builder *b, nir_ssa_def *index, struct ray_query_vars *vars
          nir_pop_if(b, NULL);
 
          rq_store_var(b, index, vars->trav.stack,
-                      nir_iadd_imm(b, rq_load_var(b, index, vars->trav.stack), 1), 1);
+                      nir_iadd_imm(b, rq_load_var(b, index, vars->trav.stack), -1), 1);
 
          nir_ssa_def *bvh_node =
             rq_load_array(b, index, vars->stack, rq_load_var(b, index, vars->trav.stack));

src/amd/vulkan/radv_pipeline.c

@@ -3058,9 +3058,9 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
       key.ps.is_int10 = blend->col_format_is_int10;
    }
 
-   if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
-      key.vs.topology = pCreateInfo->pInputAssemblyState ? pCreateInfo->pInputAssemblyState->topology : 0;
+   key.vs.topology = pCreateInfo->pInputAssemblyState ? pCreateInfo->pInputAssemblyState->topology : 0;
 
+   if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
       const VkPipelineRasterizationStateCreateInfo *raster_info = pCreateInfo->pRasterizationState;
       const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *provoking_vtx_info =
          vk_find_struct_const(raster_info->pNext,

src/broadcom/ci/broadcom-rpi4-fails.txt

@@ -350,9 +350,6 @@ spec@oes_texture_view@rendering-formats@clear GL_RGB10_A2 as GL_RG16F,Fail
 spec@oes_texture_view@rendering-formats@clear GL_RGB10_A2 as GL_RG16I,Fail
 spec@oes_texture_view@rendering-formats@clear GL_RGB10_A2 as GL_RGBA8I,Fail
 
-# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3510
-dEQP-VK.api.external.semaphore.opaque_fd.info_timeline,Fail
-
 dEQP-VK.draw.renderpass.inverted_depth_ranges.nodepthclamp_deltazero,Fail
 
 # Works if using V3D_DEBUG=noloopunroll

src/broadcom/drm-shim/meson.build

@@ -19,7 +19,7 @@
 # SOFTWARE.
 
 libvc4_noop_drm_shim = shared_library(
-  ['vc4_noop_drm_shim'],
+  'vc4_noop_drm_shim',
   'vc4_noop.c',
   include_directories: [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_gallium_aux],
   dependencies: dep_drm_shim,
@@ -28,10 +28,10 @@ libvc4_noop_drm_shim = shared_library(
 )
 
 libv3d_noop_drm_shim = shared_library(
-  ['v3d_noop_drm_shim'],
+  'v3d_noop_drm_shim',
   'v3d_noop.c',
   include_directories: [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_gallium_aux],
   dependencies: dep_drm_shim,
   gnu_symbol_visibility : 'hidden',
   install : true,
-)
\ No newline at end of file
+)

src/compiler/nir/nir_linking_helpers.c

@@ -1391,8 +1391,10 @@ nir_link_opt_varyings(nir_shader *producer, nir_shader *consumer)
             /* The varying is loaded from same uniform, so no need to do any
              * interpolation. Mark it as flat explicitly.
              */
-            if (in_var && in_var->data.interpolation <= INTERP_MODE_NOPERSPECTIVE)
+            if (in_var && in_var->data.interpolation <= INTERP_MODE_NOPERSPECTIVE) {
                in_var->data.interpolation = INTERP_MODE_FLAT;
+               out_var->data.interpolation = INTERP_MODE_FLAT;
+            }
          }
       }
 

src/freedreno/drm-shim/meson.build

@@ -20,7 +20,7 @@
 # IN THE SOFTWARE.
 
 libfreedreno_noop_drm_shim = shared_library(
-  ['freedreno_noop_drm_shim'],
+  'freedreno_noop_drm_shim',
   'freedreno_noop.c',
   include_directories: [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_gallium_aux],
   dependencies: dep_drm_shim,

src/gallium/auxiliary/gallivm/lp_bld_limits.h

@@ -119,7 +119,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
       return LP_MAX_TGSI_CONST_BUFFERS;
    case PIPE_SHADER_CAP_MAX_TEMPS:
       return LP_MAX_TGSI_TEMPS;
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 1;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@@ -152,9 +152,9 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
       return 1;
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:

src/gallium/auxiliary/target-helpers/drm_helper.h

@@ -177,8 +177,7 @@ DRM_DRIVER_DESCRIPTOR_STUB(kmsro)
 #endif
 
 #ifdef GALLIUM_R300
-#include "radeon/radeon_winsys.h"
-#include "radeon/drm/radeon_drm_public.h"
+#include "winsys/radeon_winsys.h"
 #include "r300/r300_public.h"
 
 static struct pipe_screen *
@@ -196,8 +195,7 @@ DRM_DRIVER_DESCRIPTOR_STUB(r300)
 #endif
 
 #ifdef GALLIUM_R600
-#include "radeon/radeon_winsys.h"
-#include "radeon/drm/radeon_drm_public.h"
+#include "winsys/radeon_winsys.h"
 #include "r600/r600_public.h"
 
 static struct pipe_screen *

src/gallium/auxiliary/tgsi/tgsi_exec.h

@@ -452,7 +452,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
       return PIPE_MAX_CONSTANT_BUFFERS;
    case PIPE_SHADER_CAP_MAX_TEMPS:
       return TGSI_EXEC_NUM_TEMPS;
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 1;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@@ -480,11 +480,11 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
       return 1 << PIPE_SHADER_IR_TGSI;
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
       return 1;
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
       return 1;
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:

src/gallium/drivers/asahi/agx_pipe.c

@@ -921,7 +921,7 @@ agx_get_shader_param(struct pipe_screen* pscreen,
    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
       return 16;
 
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 0;
 
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
@@ -945,9 +945,9 @@ agx_get_shader_param(struct pipe_screen* pscreen,
       return !is_no16;
 
    case PIPE_SHADER_CAP_INT64_ATOMICS:
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
       return 0;

src/gallium/drivers/crocus/crocus_screen.c

@@ -484,7 +484,7 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
       return devinfo->ver >= 6 ? 16 : 1;
    case PIPE_SHADER_CAP_MAX_TEMPS:
       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 0;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@@ -520,12 +520,12 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
       return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return 1 << PIPE_SHADER_IR_NIR;
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
       return 1;
    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:

src/gallium/drivers/d3d12/d3d12_screen.cpp

@@ -457,8 +457,8 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
        */
       return PIPE_MAX_SAMPLERS;
 
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
       return 0; /* not implemented */
 
@@ -489,10 +489,10 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
       return 0; /* unsure */
 
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 0; /* not implemented */
 
    /* should only get here on unhandled cases */

src/gallium/drivers/etnaviv/etnaviv_screen.c

@@ -374,7 +374,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
       return 64; /* Max native temporaries. */
    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
       return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 1;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@@ -407,9 +407,9 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
       return shader == PIPE_SHADER_FRAGMENT
                 ? screen->specs.max_ps_uniforms * sizeof(float[4])
                 : screen->specs.max_vs_uniforms * sizeof(float[4]);
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
       return false;

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -635,7 +635,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
              sizeof(float[4]);
    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
       return is_ir3(screen) ? 16 : 1;
-   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+   case PIPE_SHADER_CAP_CONT_SUPPORTED:
       return 1;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@@ -644,9 +644,9 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
       /* a2xx compiler doesn't handle indirect: */
       return is_ir3(screen) ? 1 : 0;
    case PIPE_SHADER_CAP_SUBROUTINES:
-   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
+   case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: