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Test shift counts for int8_t and int16_t that are too large w/ explicit masks

Ian Romanick requested to merge idr/crucible:review/int8-int16-shift into main

The SPIR-V spec says:

The result is undefined if Shift is greater than the bit width of the components of Base.

However, other APIs specify that the shift count is modulo the bitwidth of Base. To achieve this in SPIR-V, translators will insert explicit masks of Shift with 7, 15, 31, or 63 depending on the type of Base.

These two tests verify that these explicit masks are respected for 8-bit and 16-bit Base.

The Intel PRMs imply that on Gen8 and earlier, Shift is implicitly masked with 31 when Base is 32-bits or smaller. Optimizations in Mesa remove explicit masks that match the size of Base (e.g., x << (y & 15) for 16-bit Base becomes just x << y) with the assumption that the native instruction will implicitly do this mask.

The Intel PRMs explicitly say that on Gen9 and later, Shift is implicitly masked with the proper mask for the size of Base.

The results of this test seem to contradict the PRMs. If the PRMs are correct, the test sould pass on every Gen9+ platform, and it should fail on Gen8. Gen7 does not support shaderInt16 or shaderInt8, and earlier platforms do not support Vulkan. However, the total list of failures is:


The 16-bit test passes on Gen8, and the 8-bit test fails on Gen8 and Gen9.

Edited by Ian Romanick

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