- Jan 09, 2023
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With only one compatible, there is no need to define it as list (items). Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/516031/ Link: https://lore.kernel.org/r/20221225115925.55337-2-krzysztof.kozlowski@linaro.org Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Add bindings for the display hardware on SM8150. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/516195/ Link: https://lore.kernel.org/r/20221229100511.979972-1-konrad.dybcio@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
Require only properties declared in given schema, which makes the code a bit more readable and easy to follow. Suggested-by:
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- Jan 05, 2023
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There's a typo in describing the core clock as an 'escape' clock. The accurate description is 'core'. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/515938/ Link: https://lore.kernel.org/r/20221223021025.1646636-4-bryan.odonoghue@linaro.org Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com>
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power-domain is required for the sc7180 dispcc GDSC but not every qcom SoC has a similar dependency for example the apq8064. Most Qcom SoC's using mdss-dsi-ctrl seem to have the ability to power-collapse the MDP without collapsing DSI. For example the qcom vendor kernel commit for apq8084, msm8226, msm8916, msm8974. https://review.carbonrom.org/plugins/gitiles/CarbonROM/android_kernel_oneplus_msm8994/+/7b5c011a770daa2811778937ed646237a28a8694 "ARM: dts: msm: add mdss gdsc supply to dsi controller device It is possible for the DSI controller to be active when MDP is power collapsed. DSI controller needs to have it's own vote for mdss gdsc to ensure that gdsc remains on in such cases." This however doesn't appear to be the case for the apq8064 so we shouldn't be marking power-domain as required in yaml checks. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Reviewed-by:
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The existing msm8916.dtsi does not depend on nor require operating points. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Reviewed-by:
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- Jan 04, 2023
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Add in missing qcom,dsi-phy-regulator-ldo-mode to the 28nm DSI PHY. When converting from .txt to .yaml we missed this one. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Reviewed-by:
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- Dec 28, 2022
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Follow other YAMLs and replace mdss name into display-subystem. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Acked-by:
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On some SoCs (hello SM6350) vdds-supply is not wired to any smd-rpm or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line, which is voted for in the DSI ctrl node. Signed-off-by:
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On some SoCs (hello SM6115) vcca-supply is not wired to any smd-rpm or rpmh regulator, but instead powered by the VDD_MX line, which is voted for in the DSI ctrl node. Signed-off-by:
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- Nov 26, 2022
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Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform. Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended due to fact on qcm2290, sm6115 and sm6125 this phy is supplied via power domain, not regulator. Signed-off-by:
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- Nov 22, 2022
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Adding in msm8939 which is based msm8916 dtsi I stumbled across a binding check complaining about the phy name for msm8916 which we were reusing for msm8939. The currently inconsistent upstream dtsi naming of "dsi" and "dsi-phy" is not captured in the yaml for this driver. The driver however doesn't care about the name of DSI phy, hence the yaml check is redundant. Both Krzysztof and Rob suggested we could drop the phy-names entirely if it really isn't a dependency. So, drop the inconsistent and unnecessary phy-names field from the yaml. Signed-off-by:
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- Nov 04, 2022
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Dmitry Baryshkov authored
Allow defining DSI OPP table inside the DSI controller node. Reviewed-by:
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QCM2290 platform uses the 14nm DSI PHY driver. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Signed-off-by:
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- Nov 02, 2022
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Dmitry Baryshkov authored
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8250 platform. Reviewed-by:
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Dmitry Baryshkov authored
Add missing device nodes (DSI, PHYs, DP/eDP) to the existing MDSS schemas. Reviewed-by:
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Dmitry Baryshkov authored
In order to make the schema more readable, split dpu-qcm2290 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by:
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Dmitry Baryshkov authored
In order to make the schema more readable, split dpu-msm8998 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by:
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Dmitry Baryshkov authored
In order to make the schema more readable, split dpu-sdm845 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by:
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Dmitry Baryshkov authored
In order to make the schema more readable, split dpu-sc7280 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by:
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Dmitry Baryshkov authored
In order to make the schema more readable, split dpu-sc7180 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by:
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Dmitry Baryshkov authored
Move properties common to all MDSS DT nodes to the mdss-common.yaml. This extends qcom,msm8998-mdss schema to allow interconnect nodes, which will be added later, once msm8998 gains interconnect support. Reviewed-by:
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Dmitry Baryshkov authored
Move properties common to all DPU DT nodes to the dpu-common.yaml. Note, this removes description of individual DPU port@ nodes. However such definitions add no additional value. The reg values do not correspond to hardware INTF indices. The driver discovers and binds these ports not paying any care for the order of these items. Thus just leave the reference to graph.yaml#/properties/ports and the description. Reviewed-by:
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Dmitry Baryshkov authored
Add interconnects required for the SDM845 MDSS device tree node. This change was made in the commit c8c61c09 ("arm64: dts: qcom: sdm845: Add interconnects property for display"), but was not reflected in the schema. Reviewed-by:
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Dmitry Baryshkov authored
Add gcc-bus clock required for the SDM845 DPU device tree node. This change was made in the commit 111c5285 ("arm64: dts: qcom: sdm845: move bus clock to mdp node for sdm845 target"), but was not reflected in the schema. Reviewed-by:
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Dmitry Baryshkov authored
Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Reviewed-by:
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- Oct 22, 2022
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Wilken Gottwalt authored
Also update the documentation accordingly. Signed-off-by:
Wilken Gottwalt <wilken.gottwalt@posteo.net> Link: https://lore.kernel.org/r/Y0FghqQCHG/cX5Jz@monster.localdomain Signed-off-by:
Guenter Roeck <linux@roeck-us.net>
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- Oct 19, 2022
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Laurent Pinchart authored
The DPSUB doesn't live in isolation, but is connected to the programmable logic for live inputs and outputs, and also has a DisplayPort output. Model all those using OF graph. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
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- Oct 18, 2022
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Milan Broz authored
Add documentation that was missing from commit 5721d4e5 ("dm verity: Add optional "try_verify_in_tasklet" feature"). Signed-off-by:
Milan Broz <gmazyland@gmail.com> Signed-off-by:
Mike Snitzer <snitzer@kernel.org>
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ZiyangZhang authored
Add documentation for user recovery feature of ublk subsystem. Signed-off-by:
ZiyangZhang <ZiyangZhang@linux.alibaba.com> Reviewed-by:
Ming Lei <ming.lei@redhat.com> Link: https://lore.kernel.org/r/20221018045346.99706-2-ZiyangZhang@linux.alibaba.com Signed-off-by:
Jens Axboe <axboe@kernel.dk>
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- Oct 17, 2022
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Dmitry Osipenko authored
Add documentation for the dynamic locking convention. The documentation tells dma-buf API users when they should take the reservation lock and when not. Acked-by:
Sumit Semwal <sumit.semwal@linaro.org> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221017172229.42269-20-dmitry.osipenko@collabora.com
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- Oct 14, 2022
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Krzysztof Kozlowski authored
Emails to Krzysztof Opasiak bounce ("Recipient address rejected: User unknown") so drop his email from maintainers of s3fwrn5 NFC bindings and driver. Signed-off-by:David S. Miller <davem@davemloft.net>
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- Oct 13, 2022
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Bagas Sanjaya authored
Commit d206cef0 ("ACPI: docs: Drop useless DSDT override documentation") removes useless DSDT override documentation. However, the commit forgets to prune the documentation entry from table of contents of ACPI admin guide documentation, hence triggers Sphinx warning: Documentation/admin-guide/acpi/index.rst:8: WARNING: toctree contains reference to nonexisting document 'admin-guide/acpi/dsdt-override' Prune the entry to fix the warning. Fixes: d206cef0 ("ACPI: docs: Drop useless DSDT override documentation") Signed-off-by:
Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Zong Li authored
Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by:
Zong Li <zong.li@sifive.com> Suggested-by:
Conor Dooley <conor.dooley@microchip.com> Suggested-by:
Ben Dooks <ben.dooks@sifive.com> Reviewed-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Pierre Gondois authored
The '-t/-T' parameters seem to have been swapped: -t/--trace[=file]: save the stopped trace to [file|timerlat_trace.txt] -T/--thread us: stop trace if the thread latency is higher than the argument in us Swap them back. Signed-off-by:
Pierre Gondois <pierre.gondois@arm.com> Acked-by:
Daniel Bristot de Oliveira <bristot@kernel.org> Link: https://lore.kernel.org/r/20221006084409.3882542-1-pierre.gondois@arm.com Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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Conor Dooley authored
The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - ima are required - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z<foo>" format where the first letter of <foo> is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions - convention says that after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - as the above is just convention, don't apply any charset restrictions to reduce future churn - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache - ditto for the numbered extensions Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by:
Andrew Jones <ajones@ventanamicro.com> Acked-by:
Guo Ren <guoren@kernel.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
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Conor Dooley authored
While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: -
Conor Dooley authored
While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by:
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- Oct 12, 2022
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Palmer Dabbelt authored
The RISC-V ISA manual used to mandate that misaligned accesses were supported in user mode, but that requirement was removed in 2018 via riscv-isa-manual commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture."). Since the Linux uABI was already frozen at that point it's just been demoted to part of the uABI, but that was never written down. Link: https://lore.kernel.org/r/20220728210715.17214-1-palmer@rivosinc.com Signed-off-by: -
Fix the interrupt order of the charger in the binding example. Fixes: 76f52f815f1a ("dt-bindings: mfd: Add MediaTek MT6370") Signed-off-by:ChiaEn Wu <chiaen_wu@richtek.com> Acked-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/fcf4e7e7594070a8698dc0d4b96e031bcaa9b3a3.1665585952.git.chiaen_wu@richtek.com Signed-off-by:
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