- Oct 04, 2022
-
-
Add the SoC name to make it more clear. Also the next generation StarFive SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver. No functional change. Signed-off-by:
Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by:
Hal Feng <hal.feng@linux.starfivetech.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930061404.5418-1-hal.feng@linux.starfivetech.com Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Move the StarFive JH7100 pinctrl driver to a new subdirectory in preparation for adding more StarFive pinctrl drivers. No functional change. Signed-off-by:
-
Pin descriptions for this chip only look like standard GPIO device tree descriptions, while in fact they contain additional data (in excess of number of cells specified in description of gpio controllers). They also refer to only pins/gpios belonging to the driver and not to arbitrary gpio in the system. Because we want to stop exporting OF-specific handlers from gpiolib-of, let's parse the pin reference ourself instead of trying to call of_get_named_gpio(). Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Tested-by:
Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by:
-
fwnode_irq_get() can return zero to indicate IRQ mapping errors. Handle this case by skipping the interrupt resource. Fixes: a1d1e0e3 ("pinctrl: nuvoton: Add driver for WPCM450") Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220927175509.15695-1-andriy.shevchenko@linux.intel.com Signed-off-by:
-
After commit 0e3db163("pinctrl: bcm: Convert drivers to use struct pingroup and PINCTRL_PINGROUP()"), no one use struct bcm6328_pingroup, so remove it. Signed-off-by:
Yuan Can <yuancan@huawei.com> Reviewed-by:
-
There is no point to allow selecting pin-controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs. There won't be a single image for ARMv7 and ARMv8/9 SoCs, so no features/options are lost. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220925112103.148836-1-krzysztof.kozlowski@linaro.org Signed-off-by:
-
devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by:
Shang XiaoJing <shangxiaojing@huawei.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Ray Jui <ray.jui@broadcom.com> Link: https://lore.kernel.org/r/20220923101038.18036-1-shangxiaojing@huawei.com Signed-off-by:
-
Before the split of gpio and pinctrl sections in their own driver, rockchip_set_mux was called in pinmux_ops.gpio_set_direction for configuring a pin in its GPIO function. This is essential for cases where pinctrl is "bypassed" by gpio consumers otherwise the GPIO function is not configured for the pin and it does not work. Such was the case for the sysfs/libgpiod userspace GPIO handling. Let's re-implement the pinmux_ops.gpio_set_direction callback so that the gpio subsystem can request from the pinctrl driver to put the pin in its GPIO function. Fixes: 9ce9a020 ("pinctrl/rockchip: drop the gpio related codes") Cc: stable@vger.kernel.org Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20220930132033.4003377-2-foss+kernel@0leil.net Signed-off-by:
-
- Sep 20, 2022
-
-
Align the function names in the cy8c95x0_pmxops() to follow the struct pinmux_ops members naming schema. Signed-off-by:
-
The push_pull member is always accessed under the mutex, hence no need to use atomic operations on it. Signed-off-by:
-
It seems that cy8c95x0_set_mux() missed serialization of IO access. And its implementation looks half-baked. Add locking to the function. Fixes: e6cbbe42 ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by:
-
In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and and prints the error name. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122208.1894769-1-yangyingliang@huawei.com Signed-off-by:
-
In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. Signed-off-by:
-
- Sep 19, 2022
-
-
Sebastian Andrzej Siewior authored
On PREEMPT_RT enabled kernels the demultiplex interrupt handler is force threaded and runs with interrupts enabled. The invocation of generic_handle_domain_irq() with interrupts enabled triggers a lockdep warning due to a non-irq safe lock acquisition. Instead of disabling interrupts on the driver level, use generic_handle_domain_irq_safe(). [ tglx: Split out from combo patch ] Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/YnkfWFzvusFFktSt@linutronix.de Link: https://bugzilla.kernel.org/show_bug.cgi?id=215954
-
Add support for qcom,pm7250b-gpio variant. Signed-off-by:
Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by:
David Collins <quic_collinsd@quicinc.com> Signed-off-by:
Anjelique Melendez <quic_amelende@quicinc.com> Acked-by:
-
The SPMI based PMICs have the HIGH and LOW GPIO output strength mappings interchanged, fix them. Signed-off-by:
-
Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2 and GPIO_MV_VIN3. GPIO_LV_VIN2 GPIOs support two input reference voltages: VIN0 and VIN1. These are typically connected to 1.8 V and 1.2 V supplies respectively. GPIO_MV_VIN3 GPIOs support three input reference voltages: VIN0, VIN1, and VIN2. These are typically connected to Vph, 1.8 V, and 1.2 V supplies respectively. Signed-off-by:
-
Commit b6d09f78 ("pinctrl: nomadik: Drop U8540/9540 support") removes the DB8540 pin controller driver and its config PINCTRL_DB8540. There is some code left-over in the generic nomadik pinctrl driver, i.e., drivers/pinctrl/nomadik/pinctrl-nomadik.{ch}, that is still around for the removed DB8540 pin controller driver. Remove this remaining dead code. This issue was discovered with ./scripts/checkkconfigsymbols.py. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220919065435.27747-1-lukas.bulwahn@gmail.com Signed-off-by:
-
Linus Walleij authoredThis makes the Nomadik GPIO irqchip immutable. Tested on the Samsung Galaxy SIII mini GT-I8190. Cc: Marc Zyngier <maz@kernel.org> Acked-by:
Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220917203036.167607-2-linus.walleij@linaro.org Signed-off-by:
-
Linus Walleij authored
The irq data passed to irc_chip handlers i the struct gpio_chip and nothing else. We are just lucky that the nomadik chip pointer is first in the struct. Use the proper dereferencing and helpers. Reported-by:
-
- Sep 14, 2022
-
-
When an external device generated a level based interrupt then the interrupt controller could miss the interrupt. The reason is that the interrupt controller can detect only link changes. In the following example, if there is a PHY that generates an interrupt then the following would happen. The GPIO detected that the interrupt line changed, and then the 'ocelot_irq_handler' was called. Here it detects which GPIO line saw the change and for that will call the following: 1. irq_mask 2. phy interrupt routine 3. irq_eoi 4. irq_unmask And this works fine for simple cases, but if the PHY generates many interrupts, for example when doing PTP timestamping, then the following could happen. Again the function 'ocelot_irq_handler' will be called and then from here the following could happen: 1. irq_mask 2. phy interrupt routine 3. irq_eoi 4. irq_unmask Right before step 3(irq_eoi), the PHY will generate another interrupt. Now the interrupt controller will acknowledge the change in the interrupt line. So we miss the interrupt. A solution will be to use 'handle_level_irq' instead of 'handle_fasteoi_irq', because for this will change routine order of handling the interrupt. 1. irq_mask 2. irq_ack 3. phy interrupt routine 4. irq_unmask And now if the PHY will generate a new interrupt before irq_unmask, the interrupt controller will detect this because it already acknowledge the change in interrupt line at step 2(irq_ack). But this is not the full solution because there is another issue. In case there are 2 PHYs that share the interrupt line. For example phy1 generates an interrupt, then the following can happen: 1.irq_mask 2.irq_ack 3.phy0 interrupt routine 4.phy1 interrupt routine 5.irq_unmask In case phy0 will generate an interrupt while clearing the interrupt source in phy1, then the interrupt line will be kept down by phy0. So the interrupt controller will not see any changes in the interrupt line. The solution here is to update 'irq_unmask' such that it can detect if the interrupt line is still active or not. And if it is active then call again the procedure to clear the interrupts. But we don't want to do it every time, only if we know that the interrupt controller has not seen already that the interrupt line has changed. While at this, add support also for IRQ_TYPE_LEVEL_LOW. Fixes: be36abb7 ("pinctrl: ocelot: add support for interrupt controller") Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220909145942.844102-1-horatiu.vultur@microchip.com Signed-off-by:
-
Add missed help information and module export name to the Microsemi Ocelot and Jaguar2 SoC. Signed-off-by:
Colin Foster <colin.foster@in-advantage.com> Link: https://lore.kernel.org/r/20220909153802.3370088-1-colin.foster@in-advantage.com Signed-off-by:
-
- Sep 09, 2022
-
-
Move the default values to the 'default' case in the switches. Signed-off-by:
-
Colin Foster authored
There are a few Ocelot chips that can contain SGPIO logic, but can be controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In the externally controlled configurations these registers are not memory-mapped. Add support for these non-memory-mapped configurations. Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220905162132.2943088-6-colin.foster@in-advantage.com
-
Colin Foster authored
As the commit message suggests, this simply adds the ability to select SGPIO pinctrl as a module. This becomes more practical when the SGPIO hardware exists on an external chip, controlled indirectly by I2C or SPI. This commit enables that level of control. Signed-off-by:
-
Colin Foster authored
There are a few Ocelot chips that contain pinctrl logic, but can be controlled externally. Specifically the VSC7511, 7512, 7513 and 7514. In the externally controlled configurations these registers are not memory-mapped. Add support for these non-memory-mapped configurations. Signed-off-by:
-
- Sep 08, 2022
-
-
fwnode_irq_get() may return all possible signed values, such as Linux error code or 0. Fix the code to handle this properly. Fixes: 1074e1d2 ("pinctrl: pistachio: Switch to use fwnode instead of") Signed-off-by:
-
The irqchip implementation used inside the gpiochips are not supposed to be changed during runtime. So let's make the one inside the spmi-gpio gpiochip immutable. This fixes the below warning during boot: gpio gpiochip0: (c440000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220830092232.168561-1-manivannan.sadhasivam@linaro.org [switched two lines as indicated by Johan] Signed-off-by:
-
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220905180034.73132-1-andriy.shevchenko@linux.intel.com Signed-off-by:
-
fwnode_irq_get() may return all possible signed values, such as Linux error code. Fix the code to handle this properly. Fixes: be2dc859 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)") Signed-off-by:
Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220906115021.8661-1-andriy.shevchenko@linux.intel.com Signed-off-by:
-
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by:
-
PINCTRL_IMX depends on OF, however the dependency is missed when selected by PINCTRL_IMX8M* (it does not follow the indirect 'select' statements), select it explicitly. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/all/202209050605.fezJUgFH-lkp@intel.com/ Fixes: 87c2a29a ("pinctrl: imx8m: kconfig: Depends on SOC_IMX8M") Signed-off-by:
Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220905224408.346425-1-francesco.dolcini@toradex.com Signed-off-by:
-
In a few comments the style is not aligned with the rest. Correct them. While at it, drop unneeded blank lines and deduplicate 'Author'. Signed-off-by:
Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-17-andriy.shevchenko@linux.intel.com Signed-off-by:
-
Make use of the GENMASK() (far less error-prone, far more concise). Signed-off-by:
-
ACPI table on Intel Galileo Gen 1 has wrong pin number for IRQ resource of the I²C GPIO expander. Since we know what that number is and luckily have GPIO bases fixed for SoC's controllers, we may use a simple DMI quirk to match the platform and retrieve GpioInt() pin on it for the expander in question. Signed-off-by:
-
Add support of the expander found on Intel Galileo Gen1 board. The platform information comes from ACPI. Signed-off-by:
-
Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Add mod_devicetable.h include. Signed-off-by:
-
The introduced callback ->pin_dbg_show() is useful for debugging. Signed-off-by:
-
Move the default values to the 'default' case in the switches. Signed-off-by:
-
Since we have pin configuration getter and setter provided, there is no need to duplicate that in the custom ->set_config(). Instead, switch to gpiochip_generic_config(). Signed-off-by:
-
