Skip to content
Snippets Groups Projects
Commit aae87364 authored by Jessica Zhang's avatar Jessica Zhang Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block


The CWB mux has its own registers and set of operations. Add dpu_hw_cwb
abstraction to allow driver to configure the CWB mux.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/629254/
Link: https://lore.kernel.org/r/20241216-concurrent-wb-v4-12-fe220297a7f0@quicinc.com


[DB: added #include <linux/bitfield.h>]
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 675c1edf
No related branches found
No related tags found
No related merge requests found
......@@ -78,6 +78,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_cdm.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_cwb.o \
disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dsc_1_2.o \
disp/dpu1/dpu_hw_interrupts.o \
......
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
*/
#include <drm/drm_managed.h>
#include "dpu_hw_cwb.h"
#include <linux/bitfield.h>
#define CWB_MUX 0x000
#define CWB_MODE 0x004
/* CWB mux block bit definitions */
#define CWB_MUX_MASK GENMASK(3, 0)
#define CWB_MODE_MASK GENMASK(2, 0)
static void dpu_hw_cwb_config(struct dpu_hw_cwb *ctx,
struct dpu_hw_cwb_setup_cfg *cwb_cfg)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
int cwb_mux_cfg = 0xF;
enum dpu_pingpong pp;
enum cwb_mode_input input;
if (!cwb_cfg)
return;
input = cwb_cfg->input;
pp = cwb_cfg->pp_idx;
if (input >= INPUT_MODE_MAX)
return;
/*
* The CWB_MUX register takes the pingpong index for the real-time
* display
*/
if ((pp != PINGPONG_NONE) && (pp < PINGPONG_MAX))
cwb_mux_cfg = FIELD_PREP(CWB_MUX_MASK, pp - PINGPONG_0);
input = FIELD_PREP(CWB_MODE_MASK, input);
DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg);
DPU_REG_WRITE(c, CWB_MODE, input);
}
/**
* dpu_hw_cwb_init() - Initializes the writeback hw driver object with cwb.
* @dev: Corresponding device for devres management
* @cfg: wb_path catalog entry for which driver object is required
* @addr: mapped register io address of MDP
* Return: Error code or allocated dpu_hw_wb context
*/
struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,
const struct dpu_cwb_cfg *cfg,
void __iomem *addr)
{
struct dpu_hw_cwb *c;
if (!addr)
return ERR_PTR(-EINVAL);
c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
c->hw.blk_addr = addr + cfg->base;
c->hw.log_mask = DPU_DBG_MASK_CWB;
c->idx = cfg->id;
c->ops.config_cwb = dpu_hw_cwb_config;
return c;
}
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
*/
#ifndef _DPU_HW_CWB_H
#define _DPU_HW_CWB_H
#include "dpu_hw_util.h"
struct dpu_hw_cwb;
enum cwb_mode_input {
INPUT_MODE_LM_OUT,
INPUT_MODE_DSPP_OUT,
INPUT_MODE_MAX
};
/**
* struct dpu_hw_cwb_setup_cfg : Describes configuration for CWB mux
* @pp_idx: Index of the real-time pinpong that the CWB mux will
* feed the CWB mux
* @input: Input tap point
*/
struct dpu_hw_cwb_setup_cfg {
enum dpu_pingpong pp_idx;
enum cwb_mode_input input;
};
/**
*
* struct dpu_hw_cwb_ops : Interface to the cwb hw driver functions
* @config_cwb: configure CWB mux
*/
struct dpu_hw_cwb_ops {
void (*config_cwb)(struct dpu_hw_cwb *ctx,
struct dpu_hw_cwb_setup_cfg *cwb_cfg);
};
/**
* struct dpu_hw_cwb : CWB mux driver object
* @base: Hardware block base structure
* @hw: Block hardware details
* @idx: CWB index
* @ops: handle to operations possible for this CWB
*/
struct dpu_hw_cwb {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
enum dpu_cwb idx;
struct dpu_hw_cwb_ops ops;
};
/**
* dpu_hw_cwb - convert base object dpu_hw_base to container
* @hw: Pointer to base hardware block
* return: Pointer to hardware block container
*/
static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw)
{
return container_of(hw, struct dpu_hw_cwb, base);
}
struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,
const struct dpu_cwb_cfg *cfg,
void __iomem *addr);
#endif /*_DPU_HW_CWB_H */
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DPU_HW_MDSS_H
......@@ -350,6 +352,7 @@ struct dpu_mdss_color {
#define DPU_DBG_MASK_DSPP (1 << 10)
#define DPU_DBG_MASK_DSC (1 << 11)
#define DPU_DBG_MASK_CDM (1 << 12)
#define DPU_DBG_MASK_CWB (1 << 13)
/**
* struct dpu_hw_tear_check - Struct contains parameters to configure
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment