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Commit 1328cb7c authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
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drm/msm/dsi: correct programming sequence for SM8350 / SM8450


According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.

Fixes: 2f9ae4e3 ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/606947/
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org
parent c7c41220
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