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  1. Mar 16, 2012
  2. Mar 13, 2012
  3. Mar 10, 2012
  4. Mar 09, 2012
  5. Mar 06, 2012
  6. Mar 02, 2012
  7. Feb 22, 2012
  8. Feb 15, 2012
    • Chris Wilson's avatar
      intel: Detect cache domain inconsistency with valgrind · 23eeb7e1
      Chris Wilson authored
      
      Every access to either the GTT or CPU pointer is supposed to be
      proceeded by a set_domain ioctl so that GEM is able to manage the cache
      domains correctly and for the following access to be coherent. Of
      course, some people explicitly want incoherent, non-blocking access
      which is going to trigger warnings by this patch but are probably better
      served by explicit suppression.
      
      v2: Also mark the pointers as inaccessible following the explicit unmap
      and implicit unmap upon return to the cache.
      
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      23eeb7e1
  9. Feb 14, 2012
  10. Feb 13, 2012
  11. Feb 11, 2012
  12. Feb 08, 2012
  13. Feb 06, 2012
  14. Feb 03, 2012
  15. Feb 02, 2012
  16. Feb 01, 2012
    • Jerome Glisse's avatar
      radeon: add surface allocator helper v10 · c51f7f0e
      Jerome Glisse authored
      
      The surface allocator is able to build complete miptree when allocating
      surface for r600/r700/evergreen/northern islands GPU family. It also
      compute bo size and alignment for render buffer, depth buffer and
      scanout buffer.
      
      v2 fix r6xx/r7xx 2D tiling width align computation
      v3 add tile split support and fix 1d texture alignment
      v4 rework to more properly support compressed format, split surface pixel
         size and surface element size in separate fields
      v5 support texture array (still issue on r6xx)
      v6 split surface value computation and mipmap tree building, rework eg
         and newer computation
      v7 add a check for tile split and 2d tiled
      v8 initialize mode value before testing it in all case, reenable
         2D macro tile mode on r6xx for cubemap and array. Fix cubemap
         to force array size to the number of face.
      v9 fix handling of stencil buffer on evergreen
      v10 on evergreen depth buffer need to have enough room for a stencil
          buffer just after depth one
      
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      c51f7f0e
    • Eugeni Dodonov's avatar
      intel: query for LLC support · 151cdcfe
      Eugeni Dodonov authored and Eugeni Dodonov's avatar Eugeni Dodonov committed
      
      This adds support for querying the kernel about the LLC support in the
      hardware.
      
      In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
      
      v2: fix the return code checking
      
      Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
      151cdcfe
  17. Jan 31, 2012
  18. Jan 30, 2012
  19. Jan 27, 2012
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