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Kenneth Graunke
mesa
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ibc-tes
78f83738
·
intel/ibc: Implement support for pushing TES inputs
·
May 12, 2020
iris-measure
a12f7d81
·
don't bother with CRCs when not measuring
·
May 13, 2020
iris-glthread-upload
fae8700e
·
iris: Implement PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE.
·
May 15, 2020
iris-screen
56ae61f0
·
use os same file description, not fstat
·
Jun 03, 2020
ibc-eu-perf
dc87226e
·
intel/ibc: Disable SIMD32 compute shaders unless required for now
·
Jun 22, 2020
ibc-nir
dad7f845
·
nir/from_ssa: Respect and populate divergence information
·
Jun 24, 2020
no16
84929685
·
intel/compiler: Use EU performance heuristic to drop SIMD16 programs
·
Jun 29, 2020
ibc-spill
a9b4e86c
·
stash
·
Jul 06, 2020
iris-shader-delete
04985b2c
·
iris: Delete shader variants when deleting the API-facing shader
·
Jul 23, 2020
ibc-spill-4
cafcf91a
·
REMOVE THIS - debugging glsl-fs-fogcoord on ICL
·
Jul 28, 2020
ibc-spill-5
380e044d
·
CI HACK: always spill <= 5 registers
·
Aug 06, 2020
ibc-int-mul
f2d40b02
·
WIP! intel/ibc: partially implement 64-bit multiplies
·
Aug 12, 2020
tgl-tilecache
9d86589e
·
intel: Set TCCNTLREG on Gen12+ too
·
Aug 17, 2020
align16-assert
2016ec61
·
intel/eu: Assert !align16 for Gen11+ in brw_set_default_access_mode
·
Aug 19, 2020
ibc-float-controls
303f48fa
·
apply sensible regions for push constants based on their type
·
Sep 18, 2020
ibc-ssa-undef-converge
64fdbd20
·
nir: Ignore convergence of undef when coalescing parallel copies
·
Sep 21, 2020
ibc-old-old
90fab1cd
·
intel/ibc: Use SAMPLE_LZ/SAMPLE_C_LZ messages for a LOD of -0.0 too.
·
Sep 21, 2020
scratch-intrin-fixes
84965f97
·
intel/fs: Fix bit-size check for store_scratch implementation.
·
Sep 22, 2020
ibc-old
fd311e88
·
intel/ibc: Mark ibc_reg g0 as const
·
Sep 23, 2020
for-matt
33ca5207
·
try removing dead dest writes
·
Sep 30, 2020
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