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Commit 46b34689 authored by Topi Pohjolainen's avatar Topi Pohjolainen
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i965/gen6: Issue direct depth stall and flush after depth clear


instead of calling unconditionally brw_emit_mi_flush() which
does:

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                PIPE_CONTROL_RENDER_TARGET_FLUSH |
                                PIPE_CONTROL_CS_STALL);

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
                                PIPE_CONTROL_CONST_CACHE_INVALIDATE);

Signed-off-by: default avatarTopi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
Reviewed-by: default avatarJason Ekstrand <jason@jlekstrand.net>
parent e6da6943
No related merge requests found
...@@ -234,7 +234,12 @@ brw_fast_clear_depth(struct gl_context *ctx) ...@@ -234,7 +234,12 @@ brw_fast_clear_depth(struct gl_context *ctx)
* by a PIPE_CONTROL command with DEPTH_STALL bit set and Then * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
* followed by Depth FLUSH' * followed by Depth FLUSH'
*/ */
brw_emit_mi_flush(brw); brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_STALL);
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL);
} }
/* Now, the HiZ buffer contains data that needs to be resolved to the depth /* Now, the HiZ buffer contains data that needs to be resolved to the depth
......
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