- Feb 22, 2016
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Emil Velikov authored
Reflect the nv50->g80 change and the new gm107_texture header. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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- Feb 21, 2016
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Marek Olšák authored
v2: handle _mesa_hash_table_insert failure other cosmetic changes Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
This will simplify implementations of binary shaders. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
This will be part of shader binaries. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
in order to decrease the shader size for a shader cache. v2: add & use SI_MAX_VS_OUTPUTS Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Shader stats from VERDE: Default scheduler: Totals: SGPRS: 491272 -> 488672 (-0.53 %) VGPRS: 289980 -> 311093 (7.28 %) Code Size: 11091656 -> 11219948 (1.16 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 1732608 -> 2246656 (29.67 %) bytes per wave Max Waves: 78063 -> 77352 (-0.91 %) Wait states: 0 -> 0 (0.00 %) Looking at some of the worst regressions, I get: - The VGPR increase seems to be caused by the fact that if PS has used less than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20. However, the wave count remains at 10 if VGPRs <= 24, so no harm there. - The scratch increase seems to be caused by SGPR spilling. The unnecessary SGPR spilling has been an ongoing issue with the compiler and it's completely fixable by rematerializing s_loads or reordering instructions. SI scheduler: Totals: SGPRS: 374848 -> 374576 (-0.07 %) VGPRS: 284456 -> 307515 (8.11 %) Code Size: 11433068 -> 11535452 (0.90 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 509952 -> 522240 (2.41 %) bytes per wave Max Waves: 79456 -> 78217 (-1.56 %) Wait states: 0 -> 0 (0.00 %) VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much and generally spills way less than the default scheduler. (522240 spills vs 2246656 spills) Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Still disabled. Only prologs & epilogs are compiled in draw calls, but each variant of those is compiled only once per process. VS is always compiled as hw VS. TES is always compiled as hw VS. LS and ES stages are always compiled on demand. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Don't use the pstipple module. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
It only exports the primitive ID. Also used by TES when it's compiled as VS. The VS input location of the primitive ID input is v2. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
This is disabled with use_monolithic_shaders = true. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
v2: unify some code into si_get_shader_binary_size Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
Prologs (shader binaries inserted before the API shader binary) need to know this, so that they won't change the input registers unintentionally. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Marek Olšák authored
LLVMBuildInsertValue will be used on return_value. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com>
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Samuel Pitoiset authored
Kepler compute support is really different than Fermi and it's not ready yet. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Changes from v3: - move the previous OP_SELP change to the previous commit Changes from v2: - make sure the op is OP_SELP when emitting the predicate and add one assert - use bld.getSSA() for mkOp2() - add cross edge between tryLockAndSetBB and joinBB Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
This OP_SELP insn will be used to handle compare and swap subops. Changes from v2: - fix logic for GK110+ Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Shared memory address space (FILE_MEMORY_SHARED) must be used instead of global memory when a shared memory area is declared. Changes from v2: - oops, do not remove TGSI_FILE_BUFFER in a switch in nv50_ir_from_tgsi.cpp Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Reduce likelihood of collision with real buffers by placing the hole at the top of the 4G area. This fixes some indirect draw+compute tests with large buffers. Suggested by Ilia Mirkin. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
When indirect compute is used, the size of the grid (in blocks) is stored as three integers inside a buffer. This requires a macro to set up GRIDDIM_YX and GRIDDIM_Z. Changes from v2: - do not launch the grid if the number of groups for a dimension is 0 Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Textures and samplers don't seem to be aliased between COMPUTE and 3D. Changes from v2: - refactor the code to share (almost) the same logic between 3d and compute Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
This is loosely based on 3D. Shader buffers are bound on c15 (the driver constbuf) at offset 0x200. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Changes from v3: - add new validation state for COMPUTE driver constbuf Changes from v2: - always bind the driver consts even if user params come in via clover Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
This will be used to invalidate 3D driver constbuf when using COMPUTE and vice-versa. This is needed because this CB contains a bunch of useful information like the addrs of shader buffers. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
Loosely based on 3D. Changs from v3: - invalidate COMPUTE CBs after validating 3D CBs because they are aliased Changes from v2: - get rid of the 's' param to nvc0_cb_bo_push() because it doesn't matter to upload constbufs for compute using the 3d chan Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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Samuel Pitoiset authored
For compute shaders, we might need to upload uniforms. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Ilia Mirkin <imirkin@alum.mit.edu>
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