- Feb 12, 2019
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Dylan Baker authored
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Dylan Baker authored
This reverts commit 8fb8ebfb.
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Dylan Baker authored
This reverts commit 378f9967. This also remove the default true argument from the a2xx nir backend, which was introduced after this commit. There should be no change in functionality.
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Dylan Baker authored
This reverts commit af07141b.
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Dylan Baker authored
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Faith Ekstrand authored
When nir_rematerialize_derefs_in_use_blocks_impl was first written, I attempted to optimize things a bit by not bothering to re-materialize the sources of deref instructions figuring that the final caller would take care of that. However, in the case of more complex deref chains where the first link or two lives in block A and then another link and the load/store_deref intrinsic live in block B it doesn't work. The code in rematerialize_deref_in_block looks at the tail of the chain, sees that it's already in block B and skips it, not realizing that part of the chain also lives in block A. The easy solution here is to just rematerialize deref sources of deref instructions as well. This may potentially lead to a few more deref instructions being created by the conditions required for that to actually happen are fairly unlikely and, thanks to the caching, it's all linear time regardless. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109603 Fixes: 7d1d1208 "nir: Add a small pass to rematerialize derefs per-block" Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (cherry picked from commit 9e6a6ef0)
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- Feb 11, 2019
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Fixes: cd56d79b "nir: check NIR_SKIP to skip passes by name" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 78169870)
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- Feb 07, 2019
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We used to pre-set a bunch of extra arguments to a texture instruction in order to force the RA to allocate a register at the boundary of 4. However with the levelZero optimization, which removes a LOD argument when it's uniformly equal to zero, we undid that logic by removing an extra argument. As a result, we could end up with insufficient alignment on the second wide texture argument. Instead we switch to a different method of achieving the same result. The logic runs during the constraint analysis of the RA, and adds unset sources as necessary right before being merged into a wide argument. Fixes MISALIGNED_REG errors in Hitman when run with bindless textures enabled on a GK208. Fixes: 9145873b ("nvc0/ir: use levelZero flag when the lod is set to 0") Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: 19.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 5de5beed)
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Kristian Høgsberg authored
We're writing to the bo and the kernel needs to know for fd_bo_cpu_prep() to work. Fixes: f93e4312 ("freedreno/a6xx: Enable blitter") Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org> (cherry picked from commit 357ea7da)
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Can happen e.g. after a phi. Fixes: a2b5cc3c "radv: enable variable pointers" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 8d171859)
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Fixes: a2b5cc3c "radv: enable variable pointers" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 830fd0ef)
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit e00d9a9a)
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Fixes: a2b5cc3c "radv: enable variable pointers" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit dbdb44d5)
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For example with VK_EXT_buffer_device_address or VK_KHR_variable_pointers. Fixes: a2b5cc3c "radv: enable variable pointers" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 00253ab2)
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Eric Engestrom authored
Fixes: 6fca1869 "g3dvl: Update XvMC unit tests." Cc: Younes Manton <younes.m@gmail.com> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 40b53a72)
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Eric Engestrom authored
Fixes: c7b65dca "xvmc: Define some Xv attribs to allow users to specify color standard and procamp" Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 110a6e18)
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- Feb 06, 2019
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Fixes: 912a9c8d Signed-off-by: Jonathan Marek <jonathan@marek.ca> Cc: 19.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 3361305f)
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- Feb 05, 2019
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Dylan Baker authored
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Emil Velikov authored
Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: 927ba12b ("anv/tests: Adding test for the state_pool padding.") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com><Paste> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit 8943eb8f)
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Michel Dänzer authored
sizeof counts the terminating null character as well, so that also contributed to the ID computed for the X11 atom. But the convention is for only the non-null characters to contribute to the atom ID. Fixes: 2e12fe42 "loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property" Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit c0a540f3)
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Marek Olšák authored
Fixes: e2b9329f "radeonsi: move remaining perfcounter code into si_perfcounter.c" (cherry picked from commit 742d6cdb)
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- Feb 04, 2019
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Danylo Piliaiev authored
Transform feedback did not set correct SO_DECL.ComponentMask for varyings packed in VARYING_SLOT_PSIZ: gl_Layer - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z gl_PointSize - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w Fixes: 36ee2fd6 "anv: Implement the basic form of VK_EXT_transform_feedback" Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 64d3b148)
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Faith Ekstrand authored
Previously, we only applied the fix to shaders with a dispatch mode of SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 instructions. If you have a SIMD8 instruction in a SIMD16 shader, neither would trigger and the restriction could still be hit. Fixes: 232ed898 "i965/fs: Register allocator shoudn't use grf127..." Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit b4f0d062)
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- Feb 01, 2019
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We need to initialize all fields in rs->prim explicitly while creating new rastpos stage. Fixes: bac85342 ("st/mesa: allow glDrawElements to work with GL_SELECT feedback") v2: Initializing all fields in rs->prim as per Ilia. Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (cherry picked from commit 69d736b1)
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- Jan 31, 2019
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Reported by Coverity: in the case of unsupported modifier request, the code does not jump to the “fail” label to destroy the acquired resource. CID: 1435704 Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com> Fixes: 45bb8f29 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.") (cherry picked from commit 90458bef)
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Emma Anholt authored
This was copy-and-paste fail, that oddly showed up in the CTS's reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i to rgba8i or reinterprets to other signed int formats. Fixes: 6281f26f ("v3d: Add support for shader_image_load_store.") (cherry picked from commit ab4d5775)
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Emma Anholt authored
One of the CTS cases tries to invalidate just stencil of packed depth/stencil, and we incorrectly lost the depth contents. Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil Fixes: 0c42b5f3 ("mesa: wire up InvalidateFramebuffer") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit db2ae511)
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Rob Clark authored
Fixes: aa0fed10 freedreno: move ir3 to common location Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 39cfdf99)
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Rob Clark authored
Fixes: b4476138 freedreno: move drm to common location Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit e252656d)
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This fixes serious stuttering in Shadow Of The Tomb Raider. Fixes: 50fd253b ("radv/winsys: Add priority handling during submit.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9c762c01)
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Reported by Coverity: in the case where there exist hardware and non-hardware queries, the code does not jump to err_free_query and leaks the query. CID: 1430194 Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com> Fixes: 9ea90ffb ("broadcom/vc4: Add support for HW perfmon") (cherry picked from commit f6e49d5a)
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Emil Velikov authored
Earlier commit addressed 7 of the 8 instances available. v2: Rebase patch back to master (by anholt) Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com> Cc: Eric Anholt <eric@anholt.net> Fixes: 300d3ae8 ("vc4: Declare the cpu pointers as being modified in NEON asm.") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 385843ac)
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- Jan 30, 2019
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Dylan Baker authored
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Dylan Baker authored
Android.mk and autotools disagree about where generated files should go, which wasn't a problem until we wanted to build a dist tarball. This corrects the problme by changing the output and include paths to be the same on android and autotools (meson already has the correct include path). Fixes: 7d7b3083 ("automake: Fix path to generated source")
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Dylan Baker authored
Fixes: e68777c8 ("autotools: Deprecate the use of autotools")
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Dylan Baker authored
It is currently impossible to build a dist tarball that works when SWR requires LLVM 6. To generate the tarball we'd need to configure with LLVM 6, which is fine. But to build the dist check we need LLVM 7, as RadeonSI and RadV require that version. Unfortunately the headers genererated with LLVM 6 don't compile with LLVM 7, the API has changed between the two versions. I weighed a couple of options here. One would be to ship an unbootstrapped tarball generated with meson. This would fix the issue by not bootstrapping, so whatever version of LLVM used would work because the SWR headers would be generated at compile time. Unfortunately this would involve some heavy modifications to the infastructure used to upload the tarballs, and I've decided not to persue this.
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- Jan 29, 2019
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Dylan Baker authored
Fixes: 6281f26f ("v3d: Add support for shader_image_load_store.") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Dylan Baker authored
Fixes: b63a1f8e ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Dylan Baker authored
Fixes: b63a1f8e ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Matt Turner authored
Use the trick of adding and then subtracting 2**52 (52 is the number of explicit mantissa bits a double-precision floating-point value has) to implement round-to-even. Cuts the number of instructions on SKL of the piglit test fs-roundEven-double.shader_test from 109 to 21. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
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