- Aug 12, 2021
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Italo Nicola authored
Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Rohan Garg <rohan.garg@collabora.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Part-of: <mesa/mesa!12309>
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Juan A. Suárez authored
When incrementing unifa address in DCE optimization, ensure that we setup correctly the current block, so the ldfunif optimization is also executed correctly. This fixes dEQP-VK.graphicsfuzz.cov-struct-float-array-mix-uniform-vectors heap-buffer overflow with address sanitizer enabled. v2 (Iago): - Save and restore current block Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!12339>
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Iago Toral authored
While this feature is optional in Vulkan 1.1 and we don't currently expose it, the CTS still requires that the entry points exist. From the Vulkan 1.1 spec: "If the VK_KHR_sampler_ycbcr_conversion extension is not supported, support for the samplerYcbcrConversion feature is optional." (...) "samplerYcbcrConversion specifies whether the implementation supports sampler YCBCR conversion. If samplerYcbcrConversion is VK_FALSE, sampler YCBCR conversion is not supported, and samplers using sampler YCBCR conversion must not be used." Fixes (with Vulkan 1.1 exposed): dEQP-VK.api.version_check.entry_points Reviewed-by:
Juan A. Suarez <jasuarez@igalia.com> Part-of: <!12338>
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Iago Toral authored
Fixes: dEQP-VK.api.pipeline.pipeline_invalid_pointers_unused_structs.graphics Reviewed-by:
Juan A. Suarez <jasuarez@igalia.com> Part-of: <!12337>
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Pierre-Eric Pelloux-Prayer authored
Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!12306>
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Pierre-Eric Pelloux-Prayer authored
Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!12306>
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Pierre-Eric Pelloux-Prayer authored
This allows this pattern: $ radeonsi-run-tests.py /tmp/foo ... reports that some piglit tests regressed ... $ radeonsi-run-tests.py -t /tmp/foo/new_baseline/sienna_cichlid-piglit-quick-fail.csv ... this only runs the test that regressed ... Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!12306>
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Pierre-Eric Pelloux-Prayer authored
Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!12306>
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Pierre-Eric Pelloux-Prayer authored
Fixes: 20055a30 ("radeonsi: add -t option to the test script") Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!12306>
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Danylo Piliaiev authored
Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by:
Hyunjun Ko <zzoon@igalia.com> Part-of: <!10434>
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Danylo Piliaiev authored
The state which could be omitted with rasterization discard enabled - is unconditionally emitted when discard is a dynamic state. It's not an optimal way, but does not intruduce much complexity. Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by:
Hyunjun Ko <zzoon@igalia.com> Part-of: <!10434>
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Danylo Piliaiev authored
Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by:
Hyunjun Ko <zzoon@igalia.com> Part-of: <!10434>
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Danylo Piliaiev authored
Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by:
Hyunjun Ko <zzoon@igalia.com> Part-of: <!10434>
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Danylo Piliaiev authored
Signed-off-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by:
Hyunjun Ko <zzoon@igalia.com> Part-of: <!10434>
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Roland Scheidegger authored
Before a73cb106, cso contexts were never reused, but now that they are we need to be extra careful that the state in the cso context and in the pipe context matches even after an unbind, since when the cso context is reused the state might otherwise get out of sync (as there is no concept of "initial state", basically cso always relied on the default values being the same both in cso and the drivers). This fixes some errors we've seen internally with lavapipe. Fixes: a73cb106 ("aux/cso: split cso_destroy_context into unbind and a destroy functions") Reviewed-By:
Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!12261>
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Hyunjun Ko authored
This allows to set VK_PRIMITIVE_TOPOLOGY_PATCH_LIST dynamically when tessellation used. If other values are set via vkCmdSetPrimitiveTopologyEXT for the case, the validation layer can detect the issue. Fixes dEQP-VK.pipeline.extended_dynamic_state.*.topology_patch* Signed-off-by:
Hyunjun Ko <zzoon@igalia.com> Reviewed-by:
Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <!12299>
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- Aug 11, 2021
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Faith Ekstrand authored
Closes: mesa/mesa#5211 Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <mesa/mesa!12308>
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Faith Ekstrand authored
Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!12308>
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Faith Ekstrand authored
Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!12308>
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Faith Ekstrand authored
drm_i915_query_perf_config::data is an unsized array and declaring a struct containing an unsized array that isn't at the end is a GNU extension which trips up Android builds. Instead, stuff both into a char array of the appropriate size. This emulates what you'd normally do to allocate one of these with malloc only on the stack. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Part-of: <!12308>
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Faith Ekstrand authored
The gfx6_gs_visitor overrides emit_urb_write_opcode but with a different function signature. This causes warnings with -Woverloaded-virtual. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Part-of: <!12308>
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Faith Ekstrand authored
Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!12308>
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Faith Ekstrand authored
Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <mesa/mesa!12308>
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Faith Ekstrand authored
They require expat which we don't have on Android. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!12308>
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Ilia Mirkin authored
There's generally not too big of a difference between 1D (default) and buffer, but can't hurt to be accurate. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!12319>
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Paulo Zanoni authored
Again, we don't need all the dependency checking, seqno incrementing and duplicate tracking for batch->bo. Just use the unchecked version. This commit is not particularly significant since it really just saves us a check in the iris_use_pinned_bo() hot path, but since we already have the helper function, why not? v2: - (turns out the answer to "why not?" is because the patch had a bug) - Call ensure_exec_obj_space() since batch batch chaining can happen and doesn't guarantee pre-reserved space (Ken). Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!12194>
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Paulo Zanoni authored
Don't use iris_use_pinned_bo(), go directly with add_bo_to_batch(), skipping every check. This allows us to early return from iris_use_pinned_bo when the workaround bo is used, saving us the call to find_validation_entry() which ends up doing nothing except iterating over every bo in the batch. Also don't bother with ensure_exec_obj_space() since we just reset the batch and this is the second BO we're adding to it. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <!12194>
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Paulo Zanoni authored
We want to add a new caller, so extract this first. v2: kflags can never contain EXEC_OBJECT_WRITE (Ken). v3: Rebase after s/gtt_offset/address/. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!12194>
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Paulo Zanoni authored
I don't see these BOs being searched for in the benchmarks I tested so I don't think this should improve anything. On the other hand, it shouldn't hurt either since it's just an extra assignment. I want to unify both places where we have this code into a single function and the lack of the bo->index assignment was the only difference between the two places. So first we make both functions the same and in the next commit we'll unify things. This should make bisecting easier in case I'm wrong. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!12194>
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Paulo Zanoni authored
The last_seqnos list is used by iris_emit_buffer_barrier_for() and as far as I can understand we don't emit barriers for the workaround bo, so don't even bother doing the atomic operations required to bump the workaround_bo seqno list. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!12194>
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Eric Engestrom authored
Part-of: <mesa/mesa!12331>
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Eric Engestrom authored
Part-of: <mesa/mesa!12331>
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Dave Airlie authored
This is the equivalent of idr's intel/fs: sel.cond writes the flags on Gfx4 and Gfx5 except for the vec4 backend. This fixes buggy rendering seen with crocus on a qt trace. v2 (idr): Trivial whitespace change. Add unit tests. v3: Fix type in comment in unit tests. Noticed by Jason and Priit. Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Iron Lake total instructions in shared programs: 8183077 -> 8184543 (0.02%) instructions in affected programs: 198990 -> 200456 (0.74%) helped: 0 HURT: 1355 HURT stats (abs) min: 1 max: 8 x̄: 1.08 x̃: 1 HURT stats (rel) min: 0.29% max: 6.00% x̄: 0.99% x̃: 0.70% 95% mean confidence interval for instructions value: 1.04 1.12 95% mean confidence interval for instructions %-change: 0.96% 1.03% Instructions are HURT. total cycles in shared programs: 238967672 -> 238962784 (<.01%) cycles in affected programs: 4666014 -> 4661126 (-0.10%) helped: 406 HURT: 314 helped stats (abs) min: 4 max: 54 x̄: 22.46 x̃: 18 helped stats (rel) min: <.01% max: 12.80% x̄: 1.82% x̃: 0.65% HURT stats (abs) min: 2 max: 112 x̄: 13.48 x̃: 12 HURT stats (rel) min: <.01% max: 7.82% x̄: 0.81% x̃: 0.16% 95% mean confidence interval for cycles value: -8.60 -4.98 95% mean confidence interval for cycles %-change: -0.87% -0.49% Cycles are helped. GM45 total instructions in shared programs: 4986888 -> 4988354 (0.03%) instructions in affected programs: 198990 -> 200456 (0.74%) helped: 0 HURT: 1355 HURT stats (abs) min: 1 max: 8 x̄: 1.08 x̃: 1 HURT stats (rel) min: 0.29% max: 6.00% x̄: 0.99% x̃: 0.70% 95% mean confidence interval for instructions value: 1.04 1.12 95% mean confidence interval for instructions %-change: 0.96% 1.03% Instructions are HURT. total cycles in shared programs: 153577826 -> 153572938 (<.01%) cycles in affected programs: 4666014 -> 4661126 (-0.10%) helped: 406 HURT: 314 helped stats (abs) min: 4 max: 54 x̄: 22.46 x̃: 18 helped stats (rel) min: <.01% max: 12.80% x̄: 1.82% x̃: 0.65% HURT stats (abs) min: 2 max: 112 x̄: 13.48 x̃: 12 HURT stats (rel) min: <.01% max: 7.82% x̄: 0.81% x̃: 0.16% 95% mean confidence interval for cycles value: -8.60 -4.98 95% mean confidence interval for cycles %-change: -0.87% -0.49% Cycles are helped. Part-of: <!12191>
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Ian Romanick authored
On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented using a separte cmpn and sel instruction. This lowering occurs in fs_vistor::lower_minmax which is called very, very late... a long, long time after the first calls to opt_cmod_propagation. As a result, conditional modifiers can be incorrectly propagated across sel.cond on those platforms. No tests were affected by this change, and I find that quite shocking. After just changing flags_written(), all of the atan tests started failing on ILK. That required the change in cmod_propagatin (and the addition of the prop_across_into_sel_gfx5 unit test). Shader-db results for ILK and GM45 are below. I looked at a couple before and after shaders... and every case that I looked at had experienced incorrect cmod propagation. This affected a LOT of apps! Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2, Gang Beasts, and on and on... :( I discovered this bug while working on a couple new optimization passes. One of the passes attempts to remove condition modifiers that are never used. The pass made no progress except on ILK and GM45. After investigating a couple of the affected shaders, I noticed that the code in those shaders looked wrong... investigation led to this cause. v2: Trivial changes in the unit tests. v3: Fix type in comment in unit tests. Noticed by Jason and Priit. v4: Tweak handling of BRW_OPCODE_SEL special case. Suggested by Jason. Fixes: df1aec76 ("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.") Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Tested-by:
Dave Airlie <airlied@redhat.com> Iron Lake total instructions in shared programs: 8180493 -> 8181781 (0.02%) instructions in affected programs: 541796 -> 543084 (0.24%) helped: 28 HURT: 1158 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50% HURT stats (abs) min: 1 max: 3 x̄: 1.14 x̃: 1 HURT stats (rel) min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23% 95% mean confidence interval for instructions value: 1.06 1.11 95% mean confidence interval for instructions %-change: 0.31% 0.38% Instructions are HURT. total cycles in shared programs: 239420470 -> 239421690 (<.01%) cycles in affected programs: 2925992 -> 2927212 (0.04%) helped: 49 HURT: 157 helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70 helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96% HURT stats (abs) min: 2 max: 48 x̄: 27.34 x̃: 24 HURT stats (rel) min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20% 95% mean confidence interval for cycles value: -0.80 12.64 95% mean confidence interval for cycles %-change: -0.31% <.01% Inconclusive result (value mean confidence interval includes 0). GM45 total instructions in shared programs: 4985517 -> 4986207 (0.01%) instructions in affected programs: 306935 -> 307625 (0.22%) helped: 14 HURT: 625 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49% HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1 HURT stats (rel) min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22% 95% mean confidence interval for instructions value: 1.04 1.12 95% mean confidence interval for instructions %-change: 0.29% 0.36% Instructions are HURT. total cycles in shared programs: 153827268 -> 153828052 (<.01%) cycles in affected programs: 1669290 -> 1670074 (0.05%) helped: 24 HURT: 84 helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67 helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94% HURT stats (abs) min: 2 max: 48 x̄: 27.71 x̃: 24 HURT stats (rel) min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14% 95% mean confidence interval for cycles value: -1.94 16.46 95% mean confidence interval for cycles %-change: -0.29% 0.11% Inconclusive result (value mean confidence interval includes 0). Part-of: <mesa/mesa!12191>
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Dave Airlie authored
Aligning the pitch to 4 bytes allows the BLT engine to be used for transfers to/from these surfaces. Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Part-of: <mesa/mesa!12329>
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Dave Airlie authored
I lost these in my conversion from i965 but they are necessary. This should fix corruption in qt fonts at seen in the minecraft launcher. Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Part-of: <mesa/mesa!12329>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!12205>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!12205>
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Alyssa Rosenzweig authored
The negative cases here did not pass before this series, showing the bug in the clamp optimization. By introducing the FCLAMP pseudo op, the bug is fixed. Let's ensure we don't regress. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!12205>
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Alyssa Rosenzweig authored
Map nir_op_fsat/etc to FCLAMP pseudo ops, instead of FADD. There are significantly fewer knobs on FCLAMP, meaning significantly fewer things to get wrong. This fixes two(!) classes of bugs: * Swizzles (failing to lower/compose swizzles on clamps) * Numerical bugs (incorrectly treating +0.0 as an additive identity) Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Cc: mesa-stable Part-of: <mesa/mesa!12205>
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