- Jun 01, 2022
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Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0. v2: squash in updates (Alex) Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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[Why] Wrong fb offset results in dmub f/w errors and white screen. [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 [How] Read aper_base from mmhub because GC is off by default v2: use BAR for passthrough (Alex) Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Switch to use the callback function to poll the reset status on IMU. Because it will have different sequency on other ASICs. v2: drop unused variable (Alex) Acked-by:
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Candice Li authored
Adjust the sequence for ras late init and separate ras reset error status from query status. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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Dillon Varone authored
[Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Charlene Liu authored
[why] Use correct clock source initialization routine for DCN32/321 Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Dillon Varone authored
[WHY&HOW] Change criteria for setting DTO source value, and always set it regardless of the signal type. Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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stanley yang authored
Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com>
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Aurabindo Pillai authored
Disable idle optimizations until SMU can handle them to prevent DMUB timeout and subsequent system freeze Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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stanley yang authored
Fix aldebaran ras supported check on SRIOV guest side, the previous check conditicon block all ras feature on baremetal Signed-off-by:
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Alvin Lee authored
Add support for watermark table transfers. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Dillon Varone authored
Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Dillon Varone authored
[WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by:
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Huang Rui authored
IMU has two work mode such as debug mode and mission mode. Current GC v11_0_0 is using the debug mode. Acked-by:
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- May 31, 2022
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Eric Bernstein authored
Use DTBCLK for valid pixel clock generation Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by:
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Dillon Varone authored
[Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by:
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Aurabindo Pillai authored
GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are most efficient for the hardware. v2: microtiling fix noticed by Marek v3: keep Z tiling check Signed-off-by:
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Kenneth Feng authored
align the cg and pg settings between gc_v11_0 and gc_v11_2 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by:
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Aurabindo Pillai authored
Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by:
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Jack Xiao authored
fix mes11 api interface. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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- May 30, 2022
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[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by:
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Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by:
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Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by:
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Aurabindo Pillai authored
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by:
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Aurabindo Pillai authored
Add support for the GPIO changes for DCN3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2.x interrupt support. Signed-off-by:
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PhilipY authored
MMU notifier callback may pass in mm with mm->mm_users==0 when process is exiting, use mmget_no_zero to avoid accessing invalid mm in deferred list work after mm is gone. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
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- May 27, 2022
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Aurabindo Pillai authored
DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by:
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Aurabindo Pillai authored
Add register headers for DCN 3.2.0 and 3.2.1. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2 asic identifiers. Signed-off-by:
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Aurabindo Pillai authored
Add new structures for DCN 3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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stanley yang authored
SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Change-Id: Ie37e35460941f1b388f4b2891ee69b8a49b24d63 Signed-off-by:
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- May 26, 2022
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Alex Deucher authored
Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 55439817 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: drm/amd#2002 Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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fuyuan peng authoredFix spelling typo in comments. Reported-by:
k2ci <kernel-bot@kylinos.cn> Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Evan Quan authored
The feature is ready with latest 78.39.0 PMFW. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
To fit the latest 78.39.0 PMFW. Signed-off-by:
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