- May 31, 2022
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Aurabindo Pillai authored
Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jack Xiao authored
fix mes11 api interface. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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- May 30, 2022
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[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by:
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Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by:
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Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by:
Jerry Zuo <jerry.zuo@amd.com> Signed-off-by:
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Aurabindo Pillai authored
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by:
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Aurabindo Pillai authored
Add support for the GPIO changes for DCN3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2.x interrupt support. Signed-off-by:
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PhilipY authored
MMU notifier callback may pass in mm with mm->mm_users==0 when process is exiting, use mmget_no_zero to avoid accessing invalid mm in deferred list work after mm is gone. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
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- May 27, 2022
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Aurabindo Pillai authored
DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by:
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Aurabindo Pillai authored
Add register headers for DCN 3.2.0 and 3.2.1. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2 asic identifiers. Signed-off-by:
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Aurabindo Pillai authored
Add new structures for DCN 3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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stanley yang authored
SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Change-Id: Ie37e35460941f1b388f4b2891ee69b8a49b24d63 Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com>
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- May 26, 2022
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Alex Deucher authored
Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 55439817 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: drm/amd#2002 Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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fuyuan peng authoredFix spelling typo in comments. Reported-by:
k2ci <kernel-bot@kylinos.cn> Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Evan Quan authored
The feature is ready with latest 78.39.0 PMFW. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
To fit the latest 78.39.0 PMFW. Signed-off-by:
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Evan Quan authored
There is some problem with average frequency reading. Thus, we switch to the target frequency reading instead. Signed-off-by:
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- May 25, 2022
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Mitchell Augustin authored
Removed trailing whitespace from end of line in amdgpu_device.c Signed-off-by:
Mitchell Augustin <kernel@mitchellaugustin.com> Signed-off-by:
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Alex Deucher authored
Use IP version rather than asic type. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
Drop extra cases in the default case. Reviewed-by:
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Jiapeng Chong authored
This symbol is not used outside of imu_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes]. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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This version brings along the following fixes: * Changes to DP LT fallback behavior to more closely match the DP standard * Added new interfaces for lut pipeline * Restore ref_dtblck value when clk struct is cleared in init_clocks * Fixes DMUB outbox trace in S4 * Fixes lingering DIO FIFO errors when DIO no longer enabled * Reads Golden Settings Table from VBIOS Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com>
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[Why] It's possible for some fallback scenarios to result in infinite looping during link training. [How] This change modifies DP LT fallback behavior to more closely match the DP standard. Keep track of the link rate during the EQ_FAIL fallback, and use it as the maximum link rate for the CR sequence. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Ilya <Ilya.Bakoulin@amd.com>
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why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Martin <martin.leung@amd.com>
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[Description] ref_dtbclk value is assigned in clk_mgr_construct, but the clks struct is cleared in init_clocks. Make sure to restore the value or we will get 0 value for ref_dtbclk in DCN31. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com>
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[Why] DMUB Outbox0 read/write pointer not sync after resumed from S4. And that caused old traces were sent to outbox. [How] Disable DMUB Outbox0 interrupt and clear DMUB Outbox0 read/write pointer when resumes from S4. And then enable Outbox0 interrupt before starts DMCUB. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Cruise Hung <Cruise.Hung@amd.com>
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[WHY] Very low rate to cause memory access issue while resetting DMCUB after the halt command was sent to it. The process of stopping fw of DMCUB may be timeout, that means it is not in idle state, such as the window frames may still be kept in cache, so reset by force will cause MMHUB hang. [HOW] After the halt command was sent, keep checking the DMCUB state until it is idle. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
hengzhou <Hengyong.Zhou@amd.com>
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[Why] When enabling an HPO stream for the first time after having previously enabled a DIO stream there may be lingering DIO FIFO errors even though the DIO is no longer enabled. These can cause display clock change to hang if we don't apply the OTG disable workaround since the ramping logic is tied to OTG on. [How] The workaround wasn't being applied in the sequence of: 1 DIO stream 0 streams 1 HPO stream because current_state has no stream or planes in its context - and it's only swapped after optimize has finished. We should be using the incoming context instead to determine whether this logic is needed or not. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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why and how: This reverts commit 8e848b1b4ee585cbe25808b4458a74e739586034. Was causing a black screen with certain blocks Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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[Why] Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table, but driver will set it to default value 0x103d1110, which causes issue in some case [How] Remove the driver code, use the value set by dmub in dp_aux_init Reviewed-by:
Sherry Wang <YAO.WANG1@amd.com>
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Alex Deucher authored
Add a beige goby PCI ID. Reviewed-by:
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lijo lazar authored
When powerplay is not enabled, return AUTO as default level. Signed-off-by:
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- May 23, 2022
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Julia Lawall authored
Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by:
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Julia Lawall authored
Spelling mistakes (triple letters) in comments. Detected with the help of Coccinelle. Signed-off-by:
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Dave Airlie authored
Submitting a cs with 0 chunks, causes an oops later, found trying to execute the wrong userspace driver. MESA_LOADER_DRIVER_OVERRIDE=v3d glxinfo [172536.665184] BUG: kernel NULL pointer dereference, address: 00000000000001d8 [172536.665188] #PF: supervisor read access in kernel mode [172536.665189] #PF: error_code(0x0000) - not-present page [172536.665191] PGD 6712a0067 P4D 6712a0067 PUD 5af9ff067 PMD 0 [172536.665195] Oops: 0000 [#1] SMP NOPTI [172536.665197] CPU: 7 PID: 2769838 Comm: glxinfo Tainted: P O 5.10.81 #1-NixOS [172536.665199] Hardware name: To be filled by O.E.M. To be filled by O.E.M./CROSSHAIR V FORMULA-Z, BIOS 2201 03/23/2015 [172536.665272] RIP: 0010:amdgpu_cs_ioctl+0x96/0x1ce0 [amdgpu] [172536.665274] Code: 75 18 00 00 4c 8b b2 88 00 00 00 8b 46 08 48 89 54 24 68 49 89 f7 4c 89 5c 24 60 31 d2 4c 89 74 24 30 85 c0 0f 85 c0 01 00 00 <48> 83 ba d8 01 00 00 00 48 8b b4 24 90 00 00 00 74 16 48 8b 46 10 [172536.665276] RSP: 0018:ffffb47c0e81bbe0 EFLAGS: 00010246 [172536.665277] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000 [172536.665278] RDX: 0000000000000000 RSI: ffffb47c0e81be28 RDI: ffffb47c0e81bd68 [172536.665279] RBP: ffff936524080010 R08: 0000000000000000 R09: ffffb47c0e81be38 [172536.665281] R10: ffff936524080010 R11: ffff936524080000 R12: ffffb47c0e81bc40 [172536.665282] R13: ffffb47c0e81be28 R14: ffff9367bc410000 R15: ffffb47c0e81be28 [172536.665283] FS: 00007fe35e05d740(0000) GS:ffff936c1edc0000(0000) knlGS:0000000000000000 [172536.665284] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [172536.665286] CR2: 00000000000001d8 CR3: 0000000532e46000 CR4: 00000000000406e0 [172536.665287] Call Trace: [172536.665322] ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] [172536.665332] drm_ioctl_kernel+0xaa/0xf0 [drm] [172536.665338] drm_ioctl+0x201/0x3b0 [drm] [172536.665369] ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] [172536.665372] ? selinux_file_ioctl+0x135/0x230 [172536.665399] amdgpu_drm_ioctl+0x49/0x80 [amdgpu] [172536.665403] __x64_sys_ioctl+0x83/0xb0 [172536.665406] do_syscall_64+0x33/0x40 [172536.665409] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Bug: drm/amd#2018 Signed-off-by:
Dave Airlie <airlied@redhat.com> Cc: stable@vger.kernel.org Reviewed-by:
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Alex Deucher authored
Some applications want to know whether the memory is LP or not. Reviewed-by:
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Candice Li authored
Check shared buf instead of init flag for xgmi ta shared buf init during xgmi ta initialization. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com>
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