- Jun 01, 2022
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Aurabindo Pillai authored
Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Jerry Zuo <jerry.zuo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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stanley yang authored
Fix aldebaran ras supported check on SRIOV guest side, the previous check conditicon block all ras feature on baremetal Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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Alvin Lee authored
Add support for watermark table transfers. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Dillon Varone authored
Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Dillon Varone authored
[WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by:
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Huang Rui authored
IMU has two work mode such as debug mode and mission mode. Current GC v11_0_0 is using the debug mode. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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- May 31, 2022
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Eric Bernstein authored
Use DTBCLK for valid pixel clock generation Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by:
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Dillon Varone authored
[Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by:
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Aurabindo Pillai authored
GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are most efficient for the hardware. v2: microtiling fix noticed by Marek v3: keep Z tiling check Signed-off-by:
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Kenneth Feng authored
align the cg and pg settings between gc_v11_0 and gc_v11_2 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by:
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Aurabindo Pillai authored
Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by:
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Jack Xiao authored
fix mes11 api interface. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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- May 30, 2022
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[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by:
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Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by:
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Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by:
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Aurabindo Pillai authored
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by:
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Aurabindo Pillai authored
Add support for the GPIO changes for DCN3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2.x interrupt support. Signed-off-by:
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PhilipY authored
MMU notifier callback may pass in mm with mm->mm_users==0 when process is exiting, use mmget_no_zero to avoid accessing invalid mm in deferred list work after mm is gone. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com>
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- May 27, 2022
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Aurabindo Pillai authored
DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by:
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Aurabindo Pillai authored
Add register headers for DCN 3.2.0 and 3.2.1. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2 asic identifiers. Signed-off-by:
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Aurabindo Pillai authored
Add new structures for DCN 3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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stanley yang authored
SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Change-Id: Ie37e35460941f1b388f4b2891ee69b8a49b24d63 Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com>
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- May 26, 2022
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Alex Deucher authored
Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 55439817 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: drm/amd#2002 Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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fuyuan peng authoredFix spelling typo in comments. Reported-by:
k2ci <kernel-bot@kylinos.cn> Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Evan Quan authored
The feature is ready with latest 78.39.0 PMFW. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
To fit the latest 78.39.0 PMFW. Signed-off-by:
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Evan Quan authored
There is some problem with average frequency reading. Thus, we switch to the target frequency reading instead. Signed-off-by:
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- May 25, 2022
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Mitchell Augustin authored
Removed trailing whitespace from end of line in amdgpu_device.c Signed-off-by:
Mitchell Augustin <kernel@mitchellaugustin.com> Signed-off-by:
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Alex Deucher authored
Use IP version rather than asic type. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
Drop extra cases in the default case. Reviewed-by:
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Jiapeng Chong authored
This symbol is not used outside of imu_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes]. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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This version brings along the following fixes: * Changes to DP LT fallback behavior to more closely match the DP standard * Added new interfaces for lut pipeline * Restore ref_dtblck value when clk struct is cleared in init_clocks * Fixes DMUB outbox trace in S4 * Fixes lingering DIO FIFO errors when DIO no longer enabled * Reads Golden Settings Table from VBIOS Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com>
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[Why] It's possible for some fallback scenarios to result in infinite looping during link training. [How] This change modifies DP LT fallback behavior to more closely match the DP standard. Keep track of the link rate during the EQ_FAIL fallback, and use it as the maximum link rate for the CR sequence. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Ilya <Ilya.Bakoulin@amd.com>
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why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Martin <martin.leung@amd.com>
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[Description] ref_dtbclk value is assigned in clk_mgr_construct, but the clks struct is cleared in init_clocks. Make sure to restore the value or we will get 0 value for ref_dtbclk in DCN31. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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