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drm/i915/guc/slpc: Cache platform frequency limits
Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. v2: Address review comments (Michal W) v3: Formatting (Michal W) v4: Add separate function to parse rp values (Michal W) v5: Perform range checking for set min/max (Michal W) v6: checkpatch() and rename static functions (Michal W) v7: check ret code while setting SLPC limits (Michal W) Signed-off-by:Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-12-vinay.belgaumkar@intel.com
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- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 139 additions, 0 deletionsdrivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h 9 additions, 0 deletionsdrivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
- drivers/gpu/drm/i915/i915_reg.h 3 additions, 0 deletionsdrivers/gpu/drm/i915/i915_reg.h
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