- Aug 18, 2023
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Do some strict error checking so that we don't fail silently and get confused if the kernel claims to support it.
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Without implicit sync we might unmap these buffers immediately. Better make sure they are not in use. I think this is uncommon enough that we can just wait instead of setting up async delete functionality.
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Without implicit sync sparse mappings don't wait on previous submissions anymore, and will attempt to execute immediately. Hence we need to wait on all dependencies before executing. The sparse queue already uses a submission thread to make the app not block on this.
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WIP pending final drm minor number to be used.
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1) This better reflects the reality that we only have one timeline of sparse binding changes. 2) Allows making it a threaded queue from the start in prep of explicit sync stuff.
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Never access the image on the queue family, so no need. (Technically not sure if this is needed for Vulkan, somewhat of a backstop in case apps do it)
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None of the commands are allowed on these ...
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David Heidelberg authoredSigned-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!24772>
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It's only allowed in TCS or GS which means the src shader stage value is always FALSE. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!24691>
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stage/previous_stage are actually useless. Signed-off-by:
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Samuel Pitoiset authored
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The number of SGPRs need to be adjusted. Signed-off-by:
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RADV clamps the number of tess patches to 40. Signed-off-by:
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Faith Ekstrand authoredReviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!24765>
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Replace all its remaining users with nir_src_rewrite(). Reviewed-by:
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Generated by the following semantic patch: @@ expression I, S, D; @@ -nir_instr_rewrite_src(I, S, nir_src_for_ssa(D)); +nir_src_rewrite(S, D); Acked-by: -
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Generated with the following semantic patch: @@ expression I, S, D; @@ -nir_instr_rewrite_src_ssa(I, S, D); +nir_src_rewrite(S, D); Acked-by: -
Use nir_src_rewrite() instead. In a couple of cases, we can even drop a switch on whether or not it's an if source. Reviewed-by:
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This helper exists for a very tiny set of use-cases but it's better to have the helper live in nir.c than hand-roll it elsewhere. Reviewed-by:
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Technically, it's possible because bcsel has more sources than mov. However, it's not worth the pain of trying to get it right. Reviewed-by:
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NIR bits were hand-typed. Driver updates done through the following semantic patch: @@ expression T, ST, D; @@ -nir_tex_instr_add_src(T, ST, nir_src_for_ssa(D)); +nir_tex_instr_add_src(T, ST, D); Reviewed-by: -
Signed-off-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!24751>
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I have no idea why a bigger size doesn't work, the hardware doesn't complain, but it turns out that uploading big shaders still causes issues with the old limit. *shrug* Fixes: 7f63d2eb ("nv50: fix code uploads bigger than 0x10000 bytes") Signed-off-by:
Karol Herbst <git@karolherbst.de> Reviewed-by:
M Henning <drawoc@darkrefraction.com> Part-of: <mesa/mesa!24758>
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- Aug 17, 2023
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Now isl_surf_supports_ccs helper handles DEBUG_NO_CCS check and isl_surf_get_hiz_surf handles DEBUG_NO_HIZ, so we don't need to check it everywhere. Signed-off-by:
Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!24731>
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Now isl_surf_supports_ccs helper handles DEBUG_NO_CCS check and isl_surf_get_hiz_surf handles DEBUG_NO_HIZ, so we don't need to check it everywhere. Signed-off-by:
Sagar Ghuge <sagar.ghuge@intel.com>
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Let's enable INTEL_DEBUG=noccs in isl_surf_supports_ccs helper and INTEL_DEBUG=nohiz in isl_surf_get_hiz_surf helper. Signed-off-by:
Sagar Ghuge <sagar.ghuge@intel.com>
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It uses a poll function that waits for a second hoping for another thread to catch up, which is not a reliable way to do synchronization. The test has been spuriously failing merges on a regular basis recently. This is issue #9222, which I'm leaving open until the author can fix the test. Fixes: 3b69b675 ("util/fossilize_db: add runtime RO foz db loading via FOZ_DBS_DYNAMIC_LIST") Part-of: <mesa/mesa!24755>
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Covers the case where the `dri2_init_screen` calls `pipe_loader_create_screen_vk` directly and not sets the device major and minor. Signed-off-by:
Igor Torrente <igor.torrente@collabora.com> Part-of: <mesa/mesa!24678>
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If the NIR_DEBUG_PRINT_INTERNAL flag is not set, don't print debugging information for internal shaders in INTEL_DEBUG=optimizer dumps. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!24684>
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1/2 run pre-merge, and a half-hour full run for nightly. Test status looks very stable so far. Part-of: <!24737>
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This makes it easier to hook workarounds for this pipe control. Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Rohan Garg <rohan.garg@intel.com> Part-of: <mesa/mesa!24690>
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This can improve performance because fewer VGPRs and SGPRs need to be initialized. Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!24732>
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This can improve performance because fewer VGPRs and SGPRs need to be initialized. Reviewed-by:
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