- Feb 18, 2021
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Icecream95 authored
Fixes Piglit OpenCl test image-write-2d.
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Icecream95 authored
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Icecream95 authored
Operations like ihadd will need to be lowered to other instructions before it can be lowered from 64-bit. TODO: Copy the pass lowering ihadd out of the optimisation loop instead
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Icecream95 authored
OpenCL uses ubo0 for kernel inputs.
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Icecream95 authored
TODO: Fix for all load/store types (e.g. UBOs)
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Icecream95 authored
Causes INSTR_INVALID_ENC for unknown reasons. TODO: Find out why and write a more general fix
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Icecream95 authored
Try to do 8 spill operations at once, to reduce time taken to spill. TODO: Only start batching after a few registers have already been spilt.
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Icecream95 authored
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Icecream95 authored
Similar to the "lane" modifier, but for the instruction destination instead the sources.
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Icecream95 authored
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Icecream95 authored
TODO: Why is batch->framebuffer.gpu set in the first place?
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Icecream95 authored
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Alyssa Rosenzweig authored
I cannot reproduce the issue in local runs. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Passes dEQP-GLES31.functional.fbo.no_attachments.*, it doesn't look like we need to do anything special. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Pending on kernel work. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Otherwise we get a bad RA if RT 0 = RT 3 (for example), fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d Fixes: a6f1500b ("pan/bi: Workaround BLEND precolour with explicit moves") Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Passes the relevant tests of dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.*, a few failures that seem to relate to MRT instead of this. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Passes dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.* Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Used in the LD_VAR_IMM. Wondering if preload requirements shouldn't instead be pushed from the compiler based on actual usage instead of guessing from the NIR... Fixes dEQP-GLES31.functional.shaders.multisample_interpolation.sample_qualifier.* Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Used to order fragments. With that clarified it's clear that we need to wait on slot 7 for LD_TILE too (outside the limited context of a blend shader). Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Needs to support non-blend shader operation (conversion descriptor sourced from a sysval), as well as MRT. Fixes fbfetch on Bifrost. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Don't hardcode the RT to 0. Affects ES3.0 which already exposes MRT -- despite no dEQP coverage of this particular corner case, apps could hit this in the wild on 21.0. Fixes dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_blend_func_buffer_blend_func Fixes: c7e1ef7c ("panfrost: Advertise ES3.0 on Bifrost") Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Trivial. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Icecream95 authored
Part-of: <mesa/mesa!9105>
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Icecream95 authored
v2 (Alyssa): Split out functions, support 3D/array Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
We want to be able to set a descriptor table and have the instruction pair "magically" come to be. To do so, we adjust the definition of DTSEL_IMM (deviating a bit from the architectural definition but in practice simplifying disassembly immensely) and add a scheduler lowering. This ensures DTSEL is always paired correctly. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Icecream95 authored
It won't be set for OpenCL. Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
All the same formula: calculate an address, emit a pseudoinstruction for the atomic, emit a postprocess that can be DCE'd if not needed. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by:
Icecream95 <ixn@disroot.org> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Optimizes atomic counters. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by:
Icecream95 <ixn@disroot.org> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by:
Icecream95 <ixn@disroot.org> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by:
Icecream95 <ixn@disroot.org> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
To enable scheduler lowering to an ATOM_CX pair. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by:
Icecream95 <ixn@disroot.org> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Expands to a pair *SEG_ADD/+SEG_ADD, which is used for lowering shared atomics. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
Will enable DCE of atomics. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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Alyssa Rosenzweig authored
RT#0 may not have alpha, do something safe instead of risking issues with RA later. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!9105>
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