- Dec 15, 2012
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
...rather than force the exchange. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
In case anyone ever wants to disable the default. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 14, 2012
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Chris Wilson authored
So that we can prevent feeding back a stale bo when the DRI2 client tries to swap an old buffer. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57212 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Further restrict the amount of fenced bo we try to fit into the batch to make it easier for the kernel to accommodate the request. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
It is always done at the beginning of vertex emission. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 13, 2012
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
In case we hit a path were we avoid reusing the source for the mask and leave is_affine unset for a solid mask. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Makes this 855gm much happier. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Must remember, its octal not decimal. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
As we may write preparatory instructions into the batch before checking for a flush. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 12, 2012
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Chris Wilson authored
Simplify the later checks by always populating the lists with a single, albeit unpinned, bo in the case we fail to create pinned batches. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=26345 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
If the output is unscaled, then we do not require pixel interpolation (and planar formats are exactly subsampled). References: https://bugs.freedesktop.org/show_bug.cgi?id=58185 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Fixes the flickering seen in the fishtank demo, for example. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 11, 2012
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Might be worth caching the last-known-value so we can skip the query for an old swap request. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 10, 2012
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Chris Wilson authored
The DRI2 protocol is inherently racy. Fortuituously, this can be swept under the carpet by forcing the serialisation between the DRI2 clients by using a blit for the SwapBuffers. References: https://bugs.freedesktop.org/show_bug.cgi?id=58005 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
As Jesse pointed out, it is legal for the client to request that the flip be some frame in the future even with no divisor. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
If divisor is 0 but the current MSC is behind the target, we shouldn't schedule a flip (which will occur at the next vblank) or we'll end up displaying it early and returning the wrong timestamp. Preserve the optimization though by allowing us to schedule a flip if both the divisor is 0 and the current MSC is equal to or ahead of the target; this avoids a round trip through the kernel. Reported-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Chris Wilson authored
This can happen naturally for 3-pipe config on Ivybridge or if the outputs are rearranged whilst we slept. Instead of failing to change the display on the VT, install at least a fb on the CompatOutput so that hopefully the DE can take over, or give some control to the user. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Oops, I thought the 'busy' bit was now used and apparently forgot it is used to control the periodic flushing... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
A compromise between not flushing quick enough and flushing too often, hopefully. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
If we submit a batch early (for example if the GPU is idle), then submit whatever else the client drew immediately upon completion of its blockhandler. This is required to prevent flashing due to visible delay between the clear at the start of the cycle and then the overdraw later. References: https://bugs.freedesktop.org/show_bug.cgi?id=51718 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 09, 2012
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56825 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Further experimentation... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 08, 2012
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Chris Wilson authored
The aim is to improve GPU concurrency by keeping it busy. The possible complication is that we incur more overhead due to small batches. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- Dec 07, 2012
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Previously, before every operation we would look to see if the GPU was idle and we were running under a DRI compositor. If the GPU was idle, we would flush the batch in the hope that we reduce the cost of the context switch and copy from the compositor (by completing the work earlier). However, we would complete the work far too earlier and as a result would need to flush the batch before every single operation resulting in extra overhead and reduced performance. For example, the gtkperf circles benchmark under gnome-shell/compiz would be 2x slower on Ivybridge. Reported-by: Michael Larabel <michael@phoronix.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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