Draft: Refactor opcodes

This is the next step for refactoring the x86 target code, this time the instructions. The idea is to isolate the code that belongs to each x86 target and have a common code when possible. The main changes this MR brings are:

• Add a new instruction for adding comments in the code. No more comments at the beginning of an .S file
• Split the definition of opcode from the instruction. Each target is now responsible for creating x86 instructions based on their own definition. This simplifies the logic in the common x86 code.
• Prefix properly all symbols that belong to the x86insn module.
• Have checks before generating an instruction to catch up on errors quickly
• Simplify the logic to add new X86 targets.
• Remove the size parameter when it is useless. It is only needed to differentiate between cl, cx, ecx, rxc, not for simd registers
• Sanitize the orc-target/orc-backend concepts. If in the code it is used OrcTarget, use target everywhere (MMX, SSE tests where never been run on the CI, only AVX).

The code is not complete yet, but shows the whole idea. Several errors have been found while redefining the code that are now fixed or at least identified.

Current status of opcodes

• X86
• MMX
• SSE
• AVX

Once all targets are migrated, the MR will be ready to be reviewed.