util: completely rewrite and do AMD Zen L3 cache pinning correctly
This queries the CPU cache topology correctly. Acked-by:Jose Fonseca <jfonseca@vmware.com> Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <!7054>
- src/gallium/auxiliary/util/u_threaded_context.c 3 additions, 2 deletionssrc/gallium/auxiliary/util/u_threaded_context.c
- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 3 additions, 2 deletionssrc/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 3 additions, 2 deletionssrc/gallium/winsys/radeon/drm/radeon_drm_winsys.c
- src/mesa/state_tracker/st_draw.c 1 addition, 1 deletionsrc/mesa/state_tracker/st_draw.c
- src/util/u_cpu_detect.c 92 additions, 9 deletionssrc/util/u_cpu_detect.c
- src/util/u_cpu_detect.h 9 additions, 1 deletionsrc/util/u_cpu_detect.h
- src/util/u_thread.h 1 addition, 27 deletionssrc/util/u_thread.h