GT abstraction layer

Here is where I'm landing on the layout of the GT abstraction layer. At least a couple days of hacking to refactor this so any early feedback would be appreciated.

Top level device:

/**
 * struct xe_device - Top level struct of XE device
 */
struct xe_device {
        /** @drm: drm device */
        struct drm_device drm;

        /** @info: device info */
        struct {
                /** @graphics_verx10: graphics version */
                uint8_t graphics_verx10;
                /** @is_dgfx: is discrete device */
                bool is_dgfx;
                /** @platform: XE platform enum */
                enum xe_platform platform;
                /** @devid: device ID */
                u16 devid;
                /** @revid: device revision */
                u8 revid;
        } info;

        /** @ttm: ttm device */
        struct ttm_device ttm;

        /** @mmio: mmio info for device */
        struct {
                /** @size: size of MMIO space for device */
                size_t size;
                /** @regs: pointer to MMIO space for device */
                void *regs;
        } mmio;

        /** @gt: graphics tile */
        struct xe_gt gt;
};

GT structure

/**
 * struct xe_gt - Top level struct of a graphics tile
 *
 * A graphics tile may be a physical split (duplicate pieces of silicon,
 * different GGTT + VRAM) or a virtual split (shared GGTT + VRAM). Either way
 * this structure encapsulates of everything a GT is (IRQs, MMIO, VRAM, memory
 * management, microcontrols, and a hardware set of engines).
 */
struct xe_gt {
        /** @irq_enabled: interrupts enabled on the GT */
        bool irq_enabled;
        /** @irq_lock: lock for processing irq's on the GT */
        spinlock_t irq_lock;

        /** @info: GT info */
        struct {
                /** @id: id of GT */
                u8 id;
                /** @engine_mask: mask of engines present on GT */
                u64 engine_mask;
        } info;

        /**
         * @mmio: mmio info for GT, can be subset of the global device mmio
         * space
         */
        struct {
                /** @size: size of MMIO space on GT */
                size_t size;
                /** @regs: pointer to MMIO space on GT */
                void *regs;
                /**
                 * @fw: force wake for GT, making a pointer to future proof
                 * against virtual GTs sharing FW domains
                 */
                struct xe_force_wake *fw;
        } mmio;

        /**
         * @vram: vram info for GT, multiple GTs can point to same info (virtual
         * split)
         */
        struct {
                /** @io_start: */
                resource_size_t io_start;
                /** @size: */
                resource_size_t size;
                /** @mapping: */
                void *__iomem mapping;
        } vram;

        /**
         * @mem: mem management info for GT, multiple GTs can point to same
         * objects (virtual split)
         */
        struct {
                /** @vram_mgr: VRAM TTM manager */
                struct xe_ttm_vram_mgr *vram_mgr;
                /** @gtt_mr: GTT TTM manager */
                struct xe_ttm_gtt_mgr *gtt_mgr;
                /** @ggtt: Global graphics translation table */
                struct xe_ggtt *ggtt;
        } mem;

        /** @uc: micro controllers on the GT */
        struct xe_uc uc;

        /** @hw_engines: hardware engines on the GT */
        struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
};