igt@xe_tlb@basic-tlb - crash - Received signal SIGSEGV
Stdout
Using IGT_SRANDOM=1728993030 for randomisation
Opened device: /dev/dri/card1
Starting subtest: basic-tlb
Subtest basic-tlb: CRASH (0.005s)
Stderr
Starting subtest: basic-tlb
Received signal SIGSEGV.
Stack trace:
#0 [fatal_sig_handler+0x17b]
#1 [__sigaction+0x50]
#2 [fgets+0x25]
#3 [xe_gt_stats_get_count+0x90]
#4 [__igt_unique____real_main131+0x180]
#5 [main+0x2d]
#6 [__libc_init_first+0x8a]
#7 [__libc_start_main+0x8b]
#8 [_start+0x25]
Subtest basic-tlb: CRASH (0.005s)
Dmesg
<6> [468.777195] Console: switching to colour dummy device 80x25
<6> [468.777447] [IGT] xe_tlb: executing
<6> [468.778652] [IGT] xe_tlb: starting subtest basic-tlb
<6> [468.783502] [IGT] xe_tlb: finished subtest basic-tlb, CRASH
<7> [468.786299] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [468.786392] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [468.795771] xe 0000:00:02.0: [drm:drm_client_dev_restore [drm]] intel-fbdev: ret=0
<6> [468.796061] [IGT] xe_tlb: exiting, ret=139
<6> [468.811977] Console: switching to colour frame buffer device 180x56
<7> [468.847961] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [468.848237] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [468.848444] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02