Stdout
Using IGT_SRANDOM=1714677907 for randomisation
Starting subtest: many-reload
Opened device: /dev/dri/card0
Stderr
Starting subtest: many-reload
Dmesg
<7> [277.966765] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [277.966906] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [277.966972] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<6> [278.008292] Console: switching to colour dummy device 80x25
<6> [278.008805] [IGT] xe_module_load: executing
<6> [278.010896] [IGT] xe_module_load: starting subtest many-reload
<7> [278.013362] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [278.013486] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [278.013593] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_2
<7> [278.013714] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_B
<7> [278.013830] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_C
<7> [278.013938] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_D
<7> [278.014038] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PICA_TC
<7> [278.053615] xe 0000:00:02.0: [drm:atomic_remove_fb [drm]] Disabling [PLANE:32:plane 1A] because [FB:190] is removed
<7> [278.053926] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] ddb ( 0 - 4047) -> ( 0 - 0), size 4047 -> 0
<7> [278.054025] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7,*twm,*swm,*stwm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm
<7> [278.054080] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] lines 1, 14, 14, 14, 14, 14, 0, 0, 0, 3, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [278.054130] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] blocks 24, 337, 337, 337, 337, 337, 0, 0, 38, 73, 87 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [278.054177] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] min_ddb 28, 372, 372, 372, 372, 372, 0, 0, 39, 82, 88 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [278.054222] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] [CRTC:82:pipe A] data rate 0 num active planes 0
<7> [278.054294] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 0: max bw 23530 required 0 qgv_peak_bw: 38400
<7> [278.054358] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 1: max bw 36260 required 0 qgv_peak_bw: 38400
<7> [278.054420] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 2: max bw 38000 required 0 qgv_peak_bw: 38400
<7> [278.054481] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 3: max bw 38000 required 0 qgv_peak_bw: 38400
<7> [278.054540] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] Matching peaks QGV bw: 38400 for required data rate: 0
<7> [278.054704] xe 0000:00:02.0: [drm:intel_psr_disable_locked [xe]] Disabling PSR2
<7> [278.078929] xe 0000:00:02.0: [drm:__intel_fbc_disable [xe]] Disabling FBC on [PLANE:32:plane 1A]
<7> [278.096505] xe 0000:00:02.0: [drm:drm_client_release [drm]] intel-fbdev
<7> [278.097444] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.enable (expected yes, found no)
<7> [278.097456] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [278.097460] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in cpu_transcoder (expected 0, found -1)
<7> [278.097466] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in lane_count (expected 4, found 0)
<7> [278.097472] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in dp_m_n (expected tu 64 data 6329869/8388608 link 421991/524288, found tu 0, data 0/0 link 0/0)
<7> [278.097479] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in output_types (expected 0x00000100, found 0x00000000)
<7> [278.097485] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in framestart_delay (expected 1, found 0)
<7> [278.097489] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hdisplay (expected 2880, found 0)
<7> [278.097493] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_htotal (expected 3040, found 0)
<7> [278.097497] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_start (expected 2880, found 0)
<7> [278.097501] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_end (expected 3040, found 0)
<7> [278.097506] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_start (expected 2928, found 0)
<7> [278.097510] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_end (expected 2960, found 0)
<7> [278.097514] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vdisplay (expected 1800, found 0)
<7> [278.097517] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vblank_start (expected 1800, found 0)
<7> [278.097521] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vsync_start (expected 1803, found 0)
<7> [278.097525] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vsync_end (expected 1809, found 0)
<7> [278.097528] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vtotal (expected 1906, found 0)
<7> [278.097532] xe 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vblank_end (expected 1906, found 0)