igt@xe_pm@vram-d3cold-threshold - abort - Unable to change power state from D3cold to D0, device inaccessible
<4> [104.222134] worker_thread+0x1aa/0x370
<4> [104.222142] ? __pfx_worker_thread+0x10/0x10
<4> [104.222149] kthread+0x108/0x140
<4> [104.222158] ? __pfx_kthread+0x10/0x10
<4> [104.222167] ret_from_fork+0x39/0x60
<4> [104.222177] ? __pfx_kthread+0x10/0x10
<4> [104.222186] ret_from_fork_asm+0x1b/0x30
<4> [104.222197] </TASK>
<6> [105.495649] xe 0000:03:00.0: [drm] GT0: suspended
<6> [105.741273] [IGT] xe_pm: finished subtest vram-d3cold-threshold, SUCCESS
<6> [108.487645] pcieport 0000:01:00.0: not ready 1023ms after resume; waiting
<6> [109.543664] pcieport 0000:01:00.0: not ready 2047ms after resume; waiting
<6> [111.751645] pcieport 0000:01:00.0: not ready 4095ms after resume; waiting
<6> [116.103689] pcieport 0000:01:00.0: not ready 8191ms after resume; waiting
<6> [124.551663] pcieport 0000:01:00.0: not ready 16383ms after resume; waiting
<6> [142.471651] pcieport 0000:01:00.0: not ready 32767ms after resume; waiting
<4> [177.287654] pcieport 0000:01:00.0: not ready 65535ms after resume; giving up
<3> [177.287747] pcieport 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
<3> [177.288007] pcieport 0000:02:01.0: Unable to change power state from D3cold to D0, device inaccessible
<3> [177.288064] xe 0000:03:00.0: Unable to change power state from D3cold to D0, device inaccessible
<3> [177.347675] xe 0000:03:00.0: Unable to change power state from D3cold to D0, device inaccessible
<3> [177.347692] pcieport 0000:02:04.0: Unable to change power state from D3cold to D0, device inaccessible
<3> [177.347717] pci 0000:04:00.0: Unable to change power state from D3cold to D0, device inaccessible
<7> [177.348182] xe 0000:03:00.0: [drm:drm_dp_mst_get_port_malloc [drm_display_helper]] port ffff88811a3f1000 (6)
<7> [177.348223] xe 0000:03:00.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:235:DDI A/PHY A][CRTC:80:pipe A] DP link limits: pixel clock 594000 kHz DSC off max lanes 4 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
<7> [177.348323] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp 24
<7> [177.348406] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link rate required 1782000 available 2160000
<7> [177.348491] xe 0000:03:00.0: [drm:intel_psr_compute_config [xe]] PSR disabled by flag
<7> [177.348566] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:80:pipe A] hw max bpp: 36, pipe bpp: 24, dithering: 0
<7> [177.348658] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:289:DP-5] Limiting display bpp to 24 (EDID bpp 24, max requested bpp 36, max platform bpp 36)
<7> [177.348742] xe 0000:03:00.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:248:DDI B/PHY B][CRTC:131:pipe B] DP link limits: pixel clock 241500 kHz DSC off max lanes 4 max rate 270000 max pipe_bpp 24 max link_bpp 24.0000
<7> [177.348826] xe 0000:03:00.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp [xe]] Looking for slots in range min bpp 18 max bpp 24
<7> [177.348906] xe 0000:03:00.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp [xe]] Trying bpp 24
<7> [177.348984] xe 0000:03:00.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp [xe]] Got 44 slots for pipe bpp 24 dsc 0
<7> [177.349063] [drm:drm_dp_mst_update_slots [drm_display_helper]] 8b/10b encoding format on mst_state 0xffff888118c61008
<7> [177.349084] xe 0000:03:00.0: [drm:intel_psr_compute_config [xe]] PSR disabled by flag
<7> [177.349155] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:131:pipe B] hw max bpp: 24, pipe bpp: 24, dithering: 0