Skip to content

Draft: drm/msm/dpu: support virtual wide planes

Dmitry Baryshkov requested to merge lumag/msm:test-dpu-virtual-wide into msm-next

As promised in the basic wide planes support ([1]) here comes a series supporting 2*max_linewidth for all the planes.

Note: Unlike v1 and v2 this series finally includes support for additional planes - having more planes than the number of SSPP blocks.

Note: this iteration features handling of rotation and reflection of the wide plane. However rot90 is still not tested: it is enabled on sc7280 and it only supports UBWC (tiled) framebuffers, it was quite low on my priority list.

[1] https://patchwork.freedesktop.org/series/99909/

To: Rob Clark robdclark@gmail.com To: Abhinav Kumar quic_abhinavk@quicinc.com To: Dmitry Baryshkov dmitry.baryshkov@linaro.org To: Sean Paul sean@poorly.run To: Marijn Suijten marijn.suijten@somainline.org To: David Airlie airlied@gmail.com To: Simona Vetter simona@ffwll.ch Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org

Changes in v7:

Changes in v6:

  • Renamed dpu_plane_atomic_check_nopipe() -> dpu_plane_atomic_check_nosspp() and dpu_plane_atomic_check_pipes() -> dpu_plane_atomic_check_sspp() (Abhinav)
  • In dpu_rm_reserve_sspp() replaced hweight usage with explicit type allocation (Abhinav)
  • In dpu_plane_atomic_check() set r_pipe->sspp (Jun Nie)
  • In dpu_rm_reserve_sspp() check hw_sspp->ops.setup_scaler to rule out SSPP blocks with unsupported scaler blocks (RGB, QSEED2)
  • Link to v5: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org

Changes in v5:

  • Dropped extra dpu_kms instance from dpu_plane_atomic_check() (Abhinav)
  • Use DRM_PLANE_NO_SCALING instead of (1 << 16) (Abhinav)
  • Dropped excess returns documentation for dpu_rm_reserve_sspp() (Sui Jingfeng, Abhinav)
  • best_weght -> best_weight (Abhinav)
  • Moved drm_rect_width() call back to the the patch "split dpu_plane_atomic_check()" (Abhinav)
  • Got rid of saved_fmt / saved dimensions (Abhinav)
  • Expanded the commit message to describe SSPP allocation per CRTC id (Abhinav)
  • Added comment on why the size change also causes resource reallocation (Abhinav)
  • Dropeed several last "feature" patches, leaving only SSPP reallocation and using 2 SSPPs per plane for now. The rest will be submitted separately.

Changes since v3:

  • Dropped the drm_atomic_helper_check_plane_noscale (Ville)
  • Reworked the scaling factor according to global value and then check if SSPP has scaler_blk later on.
  • Split drm_rect_fp_to_int from the rotation-related fix (Abhinav)

Changes since v2:

  • Dropped the encoder-related parts, leave all resource allocation as is (Abhinav)
  • Significantly reworked the SSPP allocation code
  • Added debugging code to dump RM state in dri/N/state

Changes since v1:

  • Fixed build error due to me missing one of fixups, it was left uncommitted.
  • Implementated proper handling of wide plane rotation & reflection.

--- b4-submit-tracking ---

This section is used internally by b4 prep for tracking purposes.

{ "series": { "revision": 7, "change-id": "20240626-dpu-virtual-wide-beefb746a900", "prefixes": [], "from-thread": "20240314000216.392549-1-dmitry.baryshkov@linaro.org", "history": { "v5": [ "20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org" ], "v6": [ "20241025-dpu-virtual-wide-v6-0-0310fd519765@linaro.org" ] } } }

Merge request reports