drm/i915/xe3lpd: Add new display power wells

Xe3's power well handling is similar to previous platforms, but there
are a few changes that need to be handled to ensure optimal power
management:
 - PGB now only depends on PG1, not PG2
 - Transcoder B is now in PG1 (was previously in PGB)
 - Transcoders C & D are now in PG2 (were previously in PGC/PGD)
 - DC states now require PG2 to be off (whereas on Xe2 it could remain
   on as a dependency of PGB, although the features inside of it could
   not be used).

Bspec: 72519, 68851
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241010224311.50133-4-matthew.s.atwood@intel.com